{"id":"https://openalex.org/W2096796895","doi":"https://doi.org/10.1109/issoc.2008.4694885","title":"Integrating high speed multipliers in Coarse Grain Reconfigurable Arrays","display_name":"Integrating high speed multipliers in Coarse Grain Reconfigurable Arrays","publication_year":2008,"publication_date":"2008-11-01","ids":{"openalex":"https://openalex.org/W2096796895","doi":"https://doi.org/10.1109/issoc.2008.4694885","mag":"2096796895"},"language":"en","primary_location":{"id":"doi:10.1109/issoc.2008.4694885","is_oa":false,"landing_page_url":"https://doi.org/10.1109/issoc.2008.4694885","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 International Symposium on System-on-Chip","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5036162735","display_name":"Stavros Georgiopoulos","orcid":null},"institutions":[{"id":"https://openalex.org/I174878644","display_name":"University of Patras","ror":"https://ror.org/017wvtq80","country_code":"GR","type":"education","lineage":["https://openalex.org/I174878644"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"Stavros Georgiopoulos","raw_affiliation_strings":["ECE Department, VLSI Laboratory, University of Patras, Patras, Greece","ECE Dept., Univ. of Patras, Patras"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"ECE Department, VLSI Laboratory, University of Patras, Patras, Greece","institution_ids":["https://openalex.org/I174878644"]},{"raw_affiliation_string":"ECE Dept., Univ. of Patras, Patras","institution_ids":["https://openalex.org/I174878644"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5052143587","display_name":"Grigoris Dimitroulakos","orcid":"https://orcid.org/0000-0001-7580-3914"},"institutions":[{"id":"https://openalex.org/I158716096","display_name":"University of Peloponnese","ror":"https://ror.org/04d4d3c02","country_code":"GR","type":"education","lineage":["https://openalex.org/I158716096"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"Grigoris Dimitroulakos","raw_affiliation_strings":["Department of Computer Science and Technology, University of Peloponnese, Tripoli, Greece","Dept. of Comput. Sci. & Technol., Univ. of Peloponnese, Tripolis"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Technology, University of Peloponnese, Tripoli, Greece","institution_ids":["https://openalex.org/I158716096"]},{"raw_affiliation_string":"Dept. of Comput. Sci. & Technol., Univ. of Peloponnese, Tripolis","institution_ids":["https://openalex.org/I158716096"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5111773679","display_name":"Costas E. Goutis","orcid":null},"institutions":[{"id":"https://openalex.org/I174878644","display_name":"University of Patras","ror":"https://ror.org/017wvtq80","country_code":"GR","type":"education","lineage":["https://openalex.org/I174878644"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"Costas E. Goutis","raw_affiliation_strings":["ECE Department, VLSI Laboratory, University of Patras, Patras, Greece","ECE Dept., Univ. of Patras, Patras"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"ECE Department, VLSI Laboratory, University of Patras, Patras, Greece","institution_ids":["https://openalex.org/I174878644"]},{"raw_affiliation_string":"ECE Dept., Univ. of Patras, Patras","institution_ids":["https://openalex.org/I174878644"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.3453,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.68625822,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"1918","issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.8362745046615601},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.785779595375061},{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.6918556690216064},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.6422725319862366},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.627333402633667},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.5974248647689819},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.5491247177124023},{"id":"https://openalex.org/keywords/realization","display_name":"Realization (probability)","score":0.5068739056587219},{"id":"https://openalex.org/keywords/clock-rate","display_name":"Clock rate","score":0.4959355294704437},{"id":"https://openalex.org/keywords/reconfigurable-computing","display_name":"Reconfigurable computing","score":0.4765073359012604},{"id":"https://openalex.org/keywords/parametric-statistics","display_name":"Parametric statistics","score":0.46307194232940674},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.46042466163635254},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.40816640853881836},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.39993178844451904},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.17615020275115967},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.12482556700706482}],"concepts":[{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.8362745046615601},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.785779595375061},{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.6918556690216064},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.6422725319862366},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.627333402633667},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.5974248647689819},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.5491247177124023},{"id":"https://openalex.org/C2781089630","wikidata":"https://www.wikidata.org/wiki/Q21856745","display_name":"Realization (probability)","level":2,"score":0.5068739056587219},{"id":"https://openalex.org/C178693496","wikidata":"https://www.wikidata.org/wiki/Q911691","display_name":"Clock rate","level":3,"score":0.4959355294704437},{"id":"https://openalex.org/C142962650","wikidata":"https://www.wikidata.org/wiki/Q240838","display_name":"Reconfigurable computing","level":3,"score":0.4765073359012604},{"id":"https://openalex.org/C117251300","wikidata":"https://www.wikidata.org/wiki/Q1849855","display_name":"Parametric statistics","level":2,"score":0.46307194232940674},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.46042466163635254},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.40816640853881836},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.39993178844451904},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.17615020275115967},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.12482556700706482},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/issoc.2008.4694885","is_oa":false,"landing_page_url":"https://doi.org/10.1109/issoc.2008.4694885","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 International Symposium on System-on-Chip","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320338080","display_name":"European Social Fund","ror":"https://ror.org/00k4n6c32"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W1559272609","https://openalex.org/W1566858073","https://openalex.org/W1584008964","https://openalex.org/W2025787141","https://openalex.org/W2075854886","https://openalex.org/W2081213150","https://openalex.org/W2110535003","https://openalex.org/W2111062328","https://openalex.org/W2125458539","https://openalex.org/W2135050419","https://openalex.org/W2157564651","https://openalex.org/W2163488221","https://openalex.org/W2506983566","https://openalex.org/W4210830821","https://openalex.org/W4250486818","https://openalex.org/W6633765384"],"related_works":["https://openalex.org/W2383333355","https://openalex.org/W2144353363","https://openalex.org/W3096456556","https://openalex.org/W4240253816","https://openalex.org/W2389325540","https://openalex.org/W3011158618","https://openalex.org/W1493975478","https://openalex.org/W1650414576","https://openalex.org/W1888803177","https://openalex.org/W2984236338"],"abstract_inverted_index":{"The":[0,125,149,162],"efficiency":[1,105],"of":[2,11,33,48,54,61,93,114,139,145,159],"a":[3],"Coarse":[4,62],"Grained":[5],"Reconfigurable":[6,64],"Array":[7,65],"architecture":[8,35,44,78,147],"in":[9,57,120,131],"terms":[10],"performance":[12,171],"and":[13,42,76,108,142,170],"hardware":[14,121],"cost":[15],"is":[16,106,127],"hard":[17],"to":[18,29],"be":[19],"determined.":[20],"Until":[21],"now,":[22],"few":[23],"case":[24],"studies":[25],"have":[26,50],"been":[27,86,152],"published":[28],"determine":[30],"the":[31,34,38,43,52,58,74,77,103,111,115,132,137,140,155,165],"impact":[32,53],"parameters":[36],"on":[37,70],"Instructions":[39],"per":[40],"Cycle":[41],"area.":[45],"However,":[46],"none":[47],"those":[49],"considered":[51],"multipliers":[55,71],"embedded":[56,174],"Processing":[59],"Elements":[60],"Grain":[63],"architectures.":[66],"This":[67],"paper":[68],"focuses":[69],"both":[72],"from":[73,101,110],"compiler":[75,100],"perspective.":[79],"An":[80],"already":[81],"existing":[82,98],"exploration":[83],"framework":[84],"has":[85,151],"used":[87,128],"for":[88,136,172],"our":[89],"study.":[90],"It":[91],"consists":[92],"two":[94],"parts:":[95],"a)":[96],"an":[97],"retargetable":[99],"which":[102],"mapping":[104],"estimated":[107],"b)":[109],"parametric":[112],"realization":[113],"coarse":[116],"grained":[117],"reconfigurable":[118],"array":[119],"description":[122],"language":[123],"(VHDL).":[124],"latter":[126],"as":[129],"input":[130],"Synopsys":[133],"Design":[134],"Compiler":[135],"estimation":[138],"area":[141],"clock":[143,168],"frequency":[144,169],"each":[146],"instance.":[148],"system":[150,166],"realized":[153],"using":[154],"0.13":[156],"mum":[157],"process":[158],"ASIC":[160],"technology.":[161],"experiments":[163],"report":[164],"area,":[167],"different":[173],"multipliers.":[175]},"counts_by_year":[],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}