{"id":"https://openalex.org/W1968145031","doi":"https://doi.org/10.1109/issoc.2007.4427438","title":"Control and datapath decoupling in the design of a NoC switch: area, power and performance implications","display_name":"Control and datapath decoupling in the design of a NoC switch: area, power and performance implications","publication_year":2007,"publication_date":"2007-11-01","ids":{"openalex":"https://openalex.org/W1968145031","doi":"https://doi.org/10.1109/issoc.2007.4427438","mag":"1968145031"},"language":"en","primary_location":{"id":"doi:10.1109/issoc.2007.4427438","is_oa":false,"landing_page_url":"https://doi.org/10.1109/issoc.2007.4427438","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2007 International Symposium on System-on-Chip","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5033660496","display_name":"Simone Medardoni","orcid":null},"institutions":[{"id":"https://openalex.org/I201324441","display_name":"University of Ferrara","ror":"https://ror.org/041zkgm14","country_code":"IT","type":"education","lineage":["https://openalex.org/I201324441"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Simone Medardoni","raw_affiliation_strings":["ENDIF, University of Ferrara, Ferrara, Italy","University of Ferrara [Ferrara]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"ENDIF, University of Ferrara, Ferrara, Italy","institution_ids":["https://openalex.org/I201324441"]},{"raw_affiliation_string":"University of Ferrara [Ferrara]","institution_ids":["https://openalex.org/I201324441"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5011268330","display_name":"Davide Bertozzi","orcid":"https://orcid.org/0000-0001-7462-4551"},"institutions":[{"id":"https://openalex.org/I201324441","display_name":"University of Ferrara","ror":"https://ror.org/041zkgm14","country_code":"IT","type":"education","lineage":["https://openalex.org/I201324441"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Davide Bertozzi","raw_affiliation_strings":["ENDIF, University of Ferrara, Ferrara, Italy","University of Ferrara [Ferrara]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"ENDIF, University of Ferrara, Ferrara, Italy","institution_ids":["https://openalex.org/I201324441"]},{"raw_affiliation_string":"University of Ferrara [Ferrara]","institution_ids":["https://openalex.org/I201324441"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5043408422","display_name":"Luca Benini","orcid":"https://orcid.org/0000-0001-8068-3806"},"institutions":[{"id":"https://openalex.org/I9360294","display_name":"University of Bologna","ror":"https://ror.org/01111rn36","country_code":"IT","type":"education","lineage":["https://openalex.org/I9360294"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Luca Benini","raw_affiliation_strings":["DEIS, University of Bologna, Bologna, Italy","DEIS, University of Bologna, 40136 Bologna, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"DEIS, University of Bologna, Bologna, Italy","institution_ids":["https://openalex.org/I9360294"]},{"raw_affiliation_string":"DEIS, University of Bologna, 40136 Bologna, Italy","institution_ids":["https://openalex.org/I9360294"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5005432629","display_name":"Enrico Macii","orcid":"https://orcid.org/0000-0001-9046-5618"},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Politecnico di Torino","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Enrico Macii","raw_affiliation_strings":["DAUIN, Politecnico di Torino, Torino, Italy","DAUIN, Politecnico di Torino, 10129 Torino, Italy#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"DAUIN, Politecnico di Torino, Torino, Italy","institution_ids":["https://openalex.org/I177477856"]},{"raw_affiliation_string":"DAUIN, Politecnico di Torino, 10129 Torino, Italy#TAB#","institution_ids":["https://openalex.org/I177477856"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.8935,"has_fulltext":false,"cited_by_count":9,"citation_normalized_percentile":{"value":0.85867834,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"150","issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.998199999332428,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9980000257492065,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/datapath","display_name":"Datapath","score":0.8493841886520386},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.7028840780258179},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6781283617019653},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.6324692964553833},{"id":"https://openalex.org/keywords/network-on-a-chip","display_name":"Network on a chip","score":0.5667439103126526},{"id":"https://openalex.org/keywords/decoupling","display_name":"Decoupling (probability)","score":0.497974157333374},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.46694648265838623},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.4649587571620941},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.4140198528766632},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.40328821539878845},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.2796780467033386},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.19962170720100403},{"id":"https://openalex.org/keywords/control-engineering","display_name":"Control engineering","score":0.157953143119812}],"concepts":[{"id":"https://openalex.org/C2781198647","wikidata":"https://www.wikidata.org/wiki/Q1633673","display_name":"Datapath","level":2,"score":0.8493841886520386},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.7028840780258179},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6781283617019653},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.6324692964553833},{"id":"https://openalex.org/C128519102","wikidata":"https://www.wikidata.org/wiki/Q339554","display_name":"Network on a chip","level":2,"score":0.5667439103126526},{"id":"https://openalex.org/C205606062","wikidata":"https://www.wikidata.org/wiki/Q5249645","display_name":"Decoupling (probability)","level":2,"score":0.497974157333374},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.46694648265838623},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.4649587571620941},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.4140198528766632},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.40328821539878845},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.2796780467033386},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.19962170720100403},{"id":"https://openalex.org/C133731056","wikidata":"https://www.wikidata.org/wiki/Q4917288","display_name":"Control engineering","level":1,"score":0.157953143119812},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.0},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/issoc.2007.4427438","is_oa":false,"landing_page_url":"https://doi.org/10.1109/issoc.2007.4427438","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2007 International Symposium on System-on-Chip","raw_type":"proceedings-article"},{"id":"pmh:oai:iris.unife.it:11392/472269","is_oa":false,"landing_page_url":"http://hdl.handle.net/11392/472269","pdf_url":null,"source":{"id":"https://openalex.org/S4306400369","display_name":"Institutional Research Information System University of Ferrara (University of Ferrara)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I201324441","host_organization_name":"University of Ferrara","host_organization_lineage":["https://openalex.org/I201324441"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.5799999833106995,"display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":22,"referenced_works":["https://openalex.org/W1544550411","https://openalex.org/W1600358781","https://openalex.org/W1946139549","https://openalex.org/W1970825017","https://openalex.org/W2090190382","https://openalex.org/W2116981307","https://openalex.org/W2117300381","https://openalex.org/W2125028861","https://openalex.org/W2129799229","https://openalex.org/W2140064132","https://openalex.org/W2145336644","https://openalex.org/W2148439886","https://openalex.org/W2153025112","https://openalex.org/W2163135024","https://openalex.org/W2165576183","https://openalex.org/W2166925534","https://openalex.org/W2171940713","https://openalex.org/W3149852784","https://openalex.org/W4242669587","https://openalex.org/W4309981097","https://openalex.org/W6672914471","https://openalex.org/W7073707567"],"related_works":["https://openalex.org/W2119527718","https://openalex.org/W2070693700","https://openalex.org/W2078880479","https://openalex.org/W2119748374","https://openalex.org/W2114514951","https://openalex.org/W1972393920","https://openalex.org/W1996820488","https://openalex.org/W3147061323","https://openalex.org/W2118796996","https://openalex.org/W2365114398"],"abstract_inverted_index":{"Networks":[0],"on":[1],"chip":[2],"are":[3],"emerging":[4],"as":[5,35],"a":[6,50,78,93],"disruptive":[7],"technology":[8,82],"to":[9,24,84,105],"tackle":[10],"the":[11,58,65,86,90,108],"problem":[12],"of":[13,56,72,92],"scalable":[14],"on-chip":[15],"communication.":[16],"An":[17],"intensive":[18],"research":[19],"effort":[20],"is":[21],"being":[22],"devoted":[23],"customizing":[25],"generic":[26],"network":[27],"building":[28],"blocks":[29],"for":[30],"specific":[31],"design":[32,74,91],"objectives":[33],"such":[34],"low-latency":[36],"or":[37],"low-power.":[38],"In":[39],"this":[40],"work,":[41],"we":[42],"identify":[43],"in":[44,89],"control":[45,70],"and":[46,68],"datapath":[47],"decoupling":[48],"inside":[49],"switch":[51,95],"architecture":[52],"an":[53],"effective":[54],"means":[55],"achieving":[57],"needed":[59],"flexibility,":[60],"while":[61,99],"taking":[62],"into":[63],"account":[64],"switching,":[66],"buffering":[67],"flow":[69],"implications":[71],"each":[73],"point.":[75],"We":[76],"deploy":[77],"65":[79],"nm":[80],"low-power":[81],"library":[83],"explore":[85],"performance-power":[87],"trade-off":[88],"NoC":[94],"with":[96,107],"area":[97],"awareness,":[98],"leveraging":[100],"placement-aware":[101],"logic":[102],"synthesis":[103],"tools":[104],"deal":[106],"predictability":[109],"challenges":[110],"posed":[111],"by":[112],"nanoscale":[113],"designs.":[114]},"counts_by_year":[],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}
