{"id":"https://openalex.org/W2535334973","doi":"https://doi.org/10.1109/issoc.2005.1595655","title":"An Effective IP Reuse Methodology for Quality System-on-Chip Design","display_name":"An Effective IP Reuse Methodology for Quality System-on-Chip Design","publication_year":2005,"publication_date":"2005-01-01","ids":{"openalex":"https://openalex.org/W2535334973","doi":"https://doi.org/10.1109/issoc.2005.1595655","mag":"2535334973"},"language":"en","primary_location":{"id":"doi:10.1109/issoc.2005.1595655","is_oa":false,"landing_page_url":"https://doi.org/10.1109/issoc.2005.1595655","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2005 International Symposium on System-on-Chip","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":null,"display_name":"Soujanna Sarkar","orcid":null},"institutions":[{"id":"https://openalex.org/I4210121626","display_name":"Signal Processing (United States)","ror":"https://ror.org/021gzyw51","country_code":"US","type":"company","lineage":["https://openalex.org/I4210121626"]},{"id":"https://openalex.org/I74760111","display_name":"Texas Instruments (United States)","ror":"https://ror.org/03vsmv677","country_code":"US","type":"company","lineage":["https://openalex.org/I74760111"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Soujanna Sarkar","raw_affiliation_strings":["Digital Signal Processing Systems Group, Texas Instruments, Bangalore, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Digital Signal Processing Systems Group, Texas Instruments, Bangalore, India","institution_ids":["https://openalex.org/I4210121626","https://openalex.org/I74760111"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5112223539","display_name":"Sanjay M. Shinde","orcid":null},"institutions":[{"id":"https://openalex.org/I4210121626","display_name":"Signal Processing (United States)","ror":"https://ror.org/021gzyw51","country_code":"US","type":"company","lineage":["https://openalex.org/I4210121626"]},{"id":"https://openalex.org/I74760111","display_name":"Texas Instruments (United States)","ror":"https://ror.org/03vsmv677","country_code":"US","type":"company","lineage":["https://openalex.org/I74760111"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sanjay Shinde","raw_affiliation_strings":["Digital Signal Processing Systems Group, Texas Instruments, Bangalore, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Digital Signal Processing Systems Group, Texas Instruments, Bangalore, India","institution_ids":["https://openalex.org/I4210121626","https://openalex.org/I74760111"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5112223540","display_name":"Subash Chandar G.","orcid":null},"institutions":[{"id":"https://openalex.org/I74760111","display_name":"Texas Instruments (United States)","ror":"https://ror.org/03vsmv677","country_code":"US","type":"company","lineage":["https://openalex.org/I74760111"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Subash Chandar G.","raw_affiliation_strings":["Texas Instrum., Bangalore"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Texas Instrum., Bangalore","institution_ids":["https://openalex.org/I74760111"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.442,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":{"value":0.63557193,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"104","last_page":"107"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9980999827384949,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/reuse","display_name":"Reuse","score":0.7754350900650024},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.644842803478241},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.5662743449211121},{"id":"https://openalex.org/keywords/time-to-market","display_name":"Time to market","score":0.49319833517074585},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.48730218410491943},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.46140068769454956},{"id":"https://openalex.org/keywords/quality","display_name":"Quality (philosophy)","score":0.459972620010376},{"id":"https://openalex.org/keywords/design-methods","display_name":"Design methods","score":0.41597163677215576},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.4041358232498169},{"id":"https://openalex.org/keywords/systems-engineering","display_name":"Systems engineering","score":0.39164677262306213},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3217132091522217},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2469967007637024},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.08484676480293274}],"concepts":[{"id":"https://openalex.org/C206588197","wikidata":"https://www.wikidata.org/wiki/Q846574","display_name":"Reuse","level":2,"score":0.7754350900650024},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.644842803478241},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.5662743449211121},{"id":"https://openalex.org/C2779229675","wikidata":"https://www.wikidata.org/wiki/Q445235","display_name":"Time to market","level":2,"score":0.49319833517074585},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.48730218410491943},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.46140068769454956},{"id":"https://openalex.org/C2779530757","wikidata":"https://www.wikidata.org/wiki/Q1207505","display_name":"Quality (philosophy)","level":2,"score":0.459972620010376},{"id":"https://openalex.org/C138852830","wikidata":"https://www.wikidata.org/wiki/Q2292993","display_name":"Design methods","level":2,"score":0.41597163677215576},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.4041358232498169},{"id":"https://openalex.org/C201995342","wikidata":"https://www.wikidata.org/wiki/Q682496","display_name":"Systems engineering","level":1,"score":0.39164677262306213},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3217132091522217},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2469967007637024},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.08484676480293274},{"id":"https://openalex.org/C548081761","wikidata":"https://www.wikidata.org/wiki/Q180388","display_name":"Waste management","level":1,"score":0.0},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0},{"id":"https://openalex.org/C111472728","wikidata":"https://www.wikidata.org/wiki/Q9471","display_name":"Epistemology","level":1,"score":0.0},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/issoc.2005.1595655","is_oa":false,"landing_page_url":"https://doi.org/10.1109/issoc.2005.1595655","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2005 International Symposium on System-on-Chip","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W21347396","https://openalex.org/W1840240127","https://openalex.org/W2006154000","https://openalex.org/W2101948575","https://openalex.org/W2115730713","https://openalex.org/W2132260473","https://openalex.org/W2142720022","https://openalex.org/W2171473631","https://openalex.org/W4230201082","https://openalex.org/W6600871046","https://openalex.org/W6677154854"],"related_works":["https://openalex.org/W2100191380","https://openalex.org/W2536819812","https://openalex.org/W2144331304","https://openalex.org/W2146527276","https://openalex.org/W1492380671","https://openalex.org/W1499275350","https://openalex.org/W2535334973","https://openalex.org/W1970558519","https://openalex.org/W1579151910","https://openalex.org/W2162257677"],"abstract_inverted_index":{"Intellectual":[0],"property":[1],"(IP)":[2],"reuse":[3],"improves":[4],"system-on-a-chip":[5],"(SoC)":[6],"design":[7,13,69,96,100,145,172],"productivity,":[8],"and":[9,15,56,139,174],"helps":[10],"to":[11,38,77,106,150,162,169],"meet":[12,170],"quality":[14,20,80,178],"time-to-market":[16],"goals.":[17],"However,":[18],"IP":[19,47,76,87,108],"issues":[21],"in":[22,53,60,73,121,143],"terms":[23],"of":[24,32,67,85,127,179],"inadequate":[25],"test":[26],"coverage,":[27],"low":[28],"power":[29],"capability,":[30],"absence":[31],"functional":[33],"features":[34],"etc.":[35],"has":[36],"led":[37],"reduced":[39],"benefits":[40],"from":[41],"reuse.":[42],"This":[43],"is":[44,48,71,148],"because":[45],"the":[46,75,78,86,94,99,107,115,129,133,137,144,158,163],"usually":[49],"designed":[50],"for":[51,131,168],"use":[52],"one":[54],"chip":[55],"later":[57],"on":[58],"(re)used":[59],"chips":[61],"having":[62],"different":[63],"requirements.":[64],"Hence,":[65],"part":[66],"SoC":[68,95,123,171],"productivity":[70],"spent":[72],"enhancing":[74,128],"desired":[79,134],"level.":[81],"As":[82],"updated":[83],"versions":[84],"may":[88],"be":[89],"released":[90],"several":[91],"times":[92],"during":[93],"phase,":[97],"managing":[98],"database":[101],"poses":[102],"challenge":[103],"with":[104],"respect":[105],"enhancements.":[109],"In":[110],"this":[111],"paper,":[112],"we":[113,118],"describe":[114],"methodology":[116],"that":[117],"successfully":[119],"followed":[120],"our":[122],"design.":[124],"It":[125,147],"consists":[126],"IPs":[130,155,165],"meeting":[132],"goals,":[135],"validating":[136],"changes":[138],"controlling":[140],"its":[141],"version":[142],"database.":[146],"required":[149],"integrate":[151],"three":[152],"mission":[153],"critical":[154],"developed":[156],"by":[157],"customer.":[159],"Certain":[160],"modifications":[161],"customer":[164],"were":[166],"called":[167],"goals":[173],"obtain":[175],"a":[176],"better":[177],"implementation.":[180]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2014,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}