{"id":"https://openalex.org/W2543767597","doi":"https://doi.org/10.1109/issoc.2004.1411188","title":"Clock generation and distribution in high-performance processors","display_name":"Clock generation and distribution in high-performance processors","publication_year":2005,"publication_date":"2005-03-31","ids":{"openalex":"https://openalex.org/W2543767597","doi":"https://doi.org/10.1109/issoc.2004.1411188","mag":"2543767597"},"language":"en","primary_location":{"id":"doi:10.1109/issoc.2004.1411188","is_oa":false,"landing_page_url":"https://doi.org/10.1109/issoc.2004.1411188","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2004 International Symposium on System-on-Chip, 2004. Proceedings.","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5037919423","display_name":"Stefan Rusu","orcid":"https://orcid.org/0000-0002-3322-9173"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"S. Rusu","raw_affiliation_strings":["Intel Corporation, USA"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, USA","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5037919423"],"corresponding_institution_ids":["https://openalex.org/I1343180700"],"apc_list":null,"apc_paid":null,"fwci":1.7784,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":{"value":0.86415744,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"207","last_page":"207"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/digital-clock-manager","display_name":"Digital clock manager","score":0.7652052640914917},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.7354269623756409},{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.7319387793540955},{"id":"https://openalex.org/keywords/timing-failure","display_name":"Timing failure","score":0.7217276692390442},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6801284551620483},{"id":"https://openalex.org/keywords/microprocessor","display_name":"Microprocessor","score":0.6742382049560547},{"id":"https://openalex.org/keywords/cpu-multiplier","display_name":"CPU multiplier","score":0.6036735773086548},{"id":"https://openalex.org/keywords/debugging","display_name":"Debugging","score":0.5805975198745728},{"id":"https://openalex.org/keywords/clock-domain-crossing","display_name":"Clock domain crossing","score":0.5536558628082275},{"id":"https://openalex.org/keywords/skew","display_name":"Skew","score":0.5501558780670166},{"id":"https://openalex.org/keywords/implementation","display_name":"Implementation","score":0.4240318238735199},{"id":"https://openalex.org/keywords/power-consumption","display_name":"Power consumption","score":0.42042621970176697},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3828057050704956},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.38118019700050354},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.35435301065444946},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.34748587012290955},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.332541286945343},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.21591335535049438},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.1804165542125702},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.10350757837295532}],"concepts":[{"id":"https://openalex.org/C113074038","wikidata":"https://www.wikidata.org/wiki/Q5276052","display_name":"Digital clock manager","level":5,"score":0.7652052640914917},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.7354269623756409},{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.7319387793540955},{"id":"https://openalex.org/C104654189","wikidata":"https://www.wikidata.org/wiki/Q7806740","display_name":"Timing failure","level":5,"score":0.7217276692390442},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6801284551620483},{"id":"https://openalex.org/C2780728072","wikidata":"https://www.wikidata.org/wiki/Q5297","display_name":"Microprocessor","level":2,"score":0.6742382049560547},{"id":"https://openalex.org/C125576049","wikidata":"https://www.wikidata.org/wiki/Q2246273","display_name":"CPU multiplier","level":5,"score":0.6036735773086548},{"id":"https://openalex.org/C168065819","wikidata":"https://www.wikidata.org/wiki/Q845566","display_name":"Debugging","level":2,"score":0.5805975198745728},{"id":"https://openalex.org/C127204226","wikidata":"https://www.wikidata.org/wiki/Q5134799","display_name":"Clock domain crossing","level":5,"score":0.5536558628082275},{"id":"https://openalex.org/C43711488","wikidata":"https://www.wikidata.org/wiki/Q7534783","display_name":"Skew","level":2,"score":0.5501558780670166},{"id":"https://openalex.org/C26713055","wikidata":"https://www.wikidata.org/wiki/Q245962","display_name":"Implementation","level":2,"score":0.4240318238735199},{"id":"https://openalex.org/C2984118289","wikidata":"https://www.wikidata.org/wiki/Q29954","display_name":"Power consumption","level":3,"score":0.42042621970176697},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3828057050704956},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.38118019700050354},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.35435301065444946},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.34748587012290955},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.332541286945343},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.21591335535049438},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.1804165542125702},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.10350757837295532},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/issoc.2004.1411188","is_oa":false,"landing_page_url":"https://doi.org/10.1109/issoc.2004.1411188","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2004 International Symposium on System-on-Chip, 2004. Proceedings.","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.7699999809265137,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2088914741","https://openalex.org/W4247180033","https://openalex.org/W2040807843","https://openalex.org/W4247089581","https://openalex.org/W3006003651","https://openalex.org/W2107880456","https://openalex.org/W2559451387","https://openalex.org/W4249038728","https://openalex.org/W2617666058","https://openalex.org/W1662010573"],"abstract_inverted_index":{"This":[0],"paper":[1],"is":[2,36],"an":[3],"overview":[4],"of":[5],"clock":[6,23,45],"generation":[7],"and":[8,25,48,56],"distribution":[9,46],"techniques,":[10],"with":[11,27,61],"emphasis":[12],"on":[13],"high-performance":[14],"microprocessor":[15],"designs.":[16],"We":[17],"describe":[18],"practical":[19,62],"techniques":[20,47,58],"to":[21],"reduce":[22],"skew":[24],"jitter,":[26],"examples":[28],"from":[29],"several":[30],"industry":[31],"leaders.":[32],"As":[33],"power":[34],"consumption":[35],"a":[37],"limiting":[38],"factor":[39],"for":[40],"all":[41],"modern":[42],"designs,":[43],"low-power":[44],"flip-flop":[49],"implementations":[50],"are":[51,59],"reviewed.":[52],"Several":[53],"clock-related":[54],"design-for-test":[55],"debug":[57],"described,":[60],"implementation":[63],"examples.":[64]},"counts_by_year":[{"year":2016,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
