{"id":"https://openalex.org/W2532457969","doi":"https://doi.org/10.1109/issoc.2004.1411139","title":"Efficient barrier synchronization mechanism for emulated shared memory NOCs","display_name":"Efficient barrier synchronization mechanism for emulated shared memory NOCs","publication_year":2005,"publication_date":"2005-03-31","ids":{"openalex":"https://openalex.org/W2532457969","doi":"https://doi.org/10.1109/issoc.2004.1411139","mag":"2532457969"},"language":"en","primary_location":{"id":"doi:10.1109/issoc.2004.1411139","is_oa":false,"landing_page_url":"https://doi.org/10.1109/issoc.2004.1411139","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2004 International Symposium on System-on-Chip, 2004. Proceedings.","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5091679053","display_name":"Martti Forsell","orcid":"https://orcid.org/0000-0003-4865-8058"},"institutions":[{"id":"https://openalex.org/I4210140777","display_name":"National Consumer Research Centre","ror":"https://ror.org/04xpj5302","country_code":"FI","type":"facility","lineage":["https://openalex.org/I133731052","https://openalex.org/I4210140777"]}],"countries":["FI"],"is_corresponding":true,"raw_author_name":"M. Forsell","raw_affiliation_strings":["KT Electronics, Oulu, Finland"],"affiliations":[{"raw_affiliation_string":"KT Electronics, Oulu, Finland","institution_ids":["https://openalex.org/I4210140777"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5091679053"],"corresponding_institution_ids":["https://openalex.org/I4210140777"],"apc_list":null,"apc_paid":null,"fwci":0.2595,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.6834368,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"33","last_page":"36"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9983000159263611,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8428515195846558},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.7095488905906677},{"id":"https://openalex.org/keywords/synchronization","display_name":"Synchronization (alternating current)","score":0.6951404213905334},{"id":"https://openalex.org/keywords/shared-memory","display_name":"Shared memory","score":0.616589367389679},{"id":"https://openalex.org/keywords/mimd","display_name":"MIMD","score":0.5877783298492432},{"id":"https://openalex.org/keywords/distributed-shared-memory","display_name":"Distributed shared memory","score":0.5088651180267334},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.42647600173950195},{"id":"https://openalex.org/keywords/mechanism","display_name":"Mechanism (biology)","score":0.41271668672561646},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.41146671772003174},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.39963841438293457},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3327803313732147},{"id":"https://openalex.org/keywords/uniform-memory-access","display_name":"Uniform memory access","score":0.31721991300582886},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.29963427782058716},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.24139806628227234},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.1418512761592865},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.13079911470413208},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.10373982787132263}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8428515195846558},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.7095488905906677},{"id":"https://openalex.org/C2778562939","wikidata":"https://www.wikidata.org/wiki/Q1298791","display_name":"Synchronization (alternating current)","level":3,"score":0.6951404213905334},{"id":"https://openalex.org/C133875982","wikidata":"https://www.wikidata.org/wiki/Q764810","display_name":"Shared memory","level":2,"score":0.616589367389679},{"id":"https://openalex.org/C21032095","wikidata":"https://www.wikidata.org/wiki/Q1149237","display_name":"MIMD","level":2,"score":0.5877783298492432},{"id":"https://openalex.org/C39528615","wikidata":"https://www.wikidata.org/wiki/Q1229610","display_name":"Distributed shared memory","level":5,"score":0.5088651180267334},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.42647600173950195},{"id":"https://openalex.org/C89611455","wikidata":"https://www.wikidata.org/wiki/Q6804646","display_name":"Mechanism (biology)","level":2,"score":0.41271668672561646},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.41146671772003174},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.39963841438293457},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3327803313732147},{"id":"https://openalex.org/C51290061","wikidata":"https://www.wikidata.org/wiki/Q1936765","display_name":"Uniform memory access","level":4,"score":0.31721991300582886},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.29963427782058716},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.24139806628227234},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.1418512761592865},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.13079911470413208},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.10373982787132263},{"id":"https://openalex.org/C127162648","wikidata":"https://www.wikidata.org/wiki/Q16858953","display_name":"Channel (broadcasting)","level":2,"score":0.0},{"id":"https://openalex.org/C111472728","wikidata":"https://www.wikidata.org/wiki/Q9471","display_name":"Epistemology","level":1,"score":0.0},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/issoc.2004.1411139","is_oa":false,"landing_page_url":"https://doi.org/10.1109/issoc.2004.1411139","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2004 International Symposium on System-on-Chip, 2004. Proceedings.","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W12415586","https://openalex.org/W1481186594","https://openalex.org/W1969008575","https://openalex.org/W2004618348","https://openalex.org/W2050487400","https://openalex.org/W2072163596","https://openalex.org/W2120490947","https://openalex.org/W2170987128","https://openalex.org/W2622728018","https://openalex.org/W2951245103","https://openalex.org/W4252896185","https://openalex.org/W6763920178"],"related_works":["https://openalex.org/W2026512611","https://openalex.org/W2339366892","https://openalex.org/W2353073543","https://openalex.org/W233533876","https://openalex.org/W2353146130","https://openalex.org/W4245497162","https://openalex.org/W1985165680","https://openalex.org/W2150064838","https://openalex.org/W2604972926","https://openalex.org/W1507921119"],"abstract_inverted_index":{"Explicit":[0],"synchronization":[1,37,64],"mechanisms":[2,38],"capable":[3],"of":[4,28],"arbitrary":[5,42],"simultaneous":[6,43],"barriers":[7,44],"are":[8,46],"needed":[9],"to":[10,40,76],"support":[11,41],"parallely":[12],"recursive":[13],"synchronous":[14,20],"MIMD":[15],"programming,":[16],"even":[17],"in":[18],"step":[19],"emulated":[21],"shared":[22],"memory":[23],"machines":[24],"(ESMM)":[25],"because":[26],"control":[27],"threads":[29],"may":[30],"privately":[31],"depend":[32],"on":[33],"input":[34],"values.":[35],"Current":[36],"fail":[39],"or":[45],"not":[47],"scalable":[48,67],"with":[49],"future":[50],"silicon":[51],"technologies.":[52],"In":[53],"this":[54],"paper,":[55],"we":[56],"propose":[57],"a":[58],"novel":[59],"constant":[60],"execution":[61],"time":[62],"barrier":[63],"mechanism":[65,73],"for":[66],"ESMMs":[68],"using":[69],"active":[70],"memory.":[71],"The":[72],"is":[74],"applied":[75],"our":[77],"Eclipse":[78],"network-on-chip":[79],"architecture":[80],"and":[81],"evaluated":[82],"briefly.":[83]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
