{"id":"https://openalex.org/W2532977569","doi":"https://doi.org/10.1109/issoc.2004.1411131","title":"Optimizing a high performance 32-bit processor for programmable logic","display_name":"Optimizing a high performance 32-bit processor for programmable logic","publication_year":2005,"publication_date":"2005-03-31","ids":{"openalex":"https://openalex.org/W2532977569","doi":"https://doi.org/10.1109/issoc.2004.1411131","mag":"2532977569"},"language":"en","primary_location":{"id":"doi:10.1109/issoc.2004.1411131","is_oa":false,"landing_page_url":"https://doi.org/10.1109/issoc.2004.1411131","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2004 International Symposium on System-on-Chip, 2004. Proceedings.","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5005702188","display_name":"Paul Metzgen","orcid":null},"institutions":[{"id":"https://openalex.org/I22433950","display_name":"Altera (United States)","ror":"https://ror.org/017b7j426","country_code":"US","type":"company","lineage":["https://openalex.org/I22433950"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"P. Metzgen","raw_affiliation_strings":["Altera Corporation, USA"],"affiliations":[{"raw_affiliation_string":"Altera Corporation, USA","institution_ids":["https://openalex.org/I22433950"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5005702188"],"corresponding_institution_ids":["https://openalex.org/I22433950"],"apc_list":null,"apc_paid":null,"fwci":1.8047,"has_fulltext":false,"cited_by_count":14,"citation_normalized_percentile":{"value":0.86373299,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"13","last_page":"13"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9958000183105469,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9958000183105469,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.991100013256073,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9825000166893005,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8578879237174988},{"id":"https://openalex.org/keywords/multiplexer","display_name":"Multiplexer","score":0.723324716091156},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7176399827003479},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6481354236602783},{"id":"https://openalex.org/keywords/flexibility","display_name":"Flexibility (engineering)","score":0.6018660068511963},{"id":"https://openalex.org/keywords/programmable-logic-device","display_name":"Programmable logic device","score":0.5523005723953247},{"id":"https://openalex.org/keywords/nios-ii","display_name":"Nios II","score":0.5486071109771729},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.5422466993331909},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.48417192697525024},{"id":"https://openalex.org/keywords/programmable-array-logic","display_name":"Programmable Array Logic","score":0.47826087474823},{"id":"https://openalex.org/keywords/logic-block","display_name":"Logic block","score":0.4563501477241516},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4443874657154083},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.4333172142505646},{"id":"https://openalex.org/keywords/programmable-logic-array","display_name":"Programmable logic array","score":0.4255679249763489},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.2718921899795532},{"id":"https://openalex.org/keywords/multiplexing","display_name":"Multiplexing","score":0.20546647906303406},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.17373132705688477}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8578879237174988},{"id":"https://openalex.org/C70970002","wikidata":"https://www.wikidata.org/wiki/Q189434","display_name":"Multiplexer","level":3,"score":0.723324716091156},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7176399827003479},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6481354236602783},{"id":"https://openalex.org/C2780598303","wikidata":"https://www.wikidata.org/wiki/Q65921492","display_name":"Flexibility (engineering)","level":2,"score":0.6018660068511963},{"id":"https://openalex.org/C206274596","wikidata":"https://www.wikidata.org/wiki/Q1063837","display_name":"Programmable logic device","level":2,"score":0.5523005723953247},{"id":"https://openalex.org/C2781190120","wikidata":"https://www.wikidata.org/wiki/Q438281","display_name":"Nios II","level":3,"score":0.5486071109771729},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.5422466993331909},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.48417192697525024},{"id":"https://openalex.org/C113323844","wikidata":"https://www.wikidata.org/wiki/Q1378651","display_name":"Programmable Array Logic","level":5,"score":0.47826087474823},{"id":"https://openalex.org/C2778325283","wikidata":"https://www.wikidata.org/wiki/Q1125244","display_name":"Logic block","level":3,"score":0.4563501477241516},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4443874657154083},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.4333172142505646},{"id":"https://openalex.org/C182322920","wikidata":"https://www.wikidata.org/wiki/Q2112217","display_name":"Programmable logic array","level":3,"score":0.4255679249763489},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.2718921899795532},{"id":"https://openalex.org/C19275194","wikidata":"https://www.wikidata.org/wiki/Q222903","display_name":"Multiplexing","level":2,"score":0.20546647906303406},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.17373132705688477},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/issoc.2004.1411131","is_oa":false,"landing_page_url":"https://doi.org/10.1109/issoc.2004.1411131","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2004 International Symposium on System-on-Chip, 2004. Proceedings.","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","score":0.49000000953674316,"id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2480852620","https://openalex.org/W2135636985","https://openalex.org/W2118828191","https://openalex.org/W2182398074","https://openalex.org/W2246445978","https://openalex.org/W3023652529","https://openalex.org/W1533253004","https://openalex.org/W4237841534","https://openalex.org/W2071567894","https://openalex.org/W2139569078"],"abstract_inverted_index":{"Summary":[0],"form":[1],"only":[2],"given.":[3],"Altera's":[4,32],"SOPC":[5,29],"Builder":[6,30],"Tool":[7],"enables":[8],"engineers":[9,138],"to":[10,52,82,103,188],"create":[11],"tailor-made":[12],"systems":[13],"in":[14,28,98,106,118,182],"an":[15,99,104,107,134,172],"FPGA":[16,86,100,180],"with":[17],"a":[18],"short":[19],"development":[20],"cycle;":[21],"one":[22],"of":[23,40,48,55,66,72,122,126,147,194],"the":[24,44,79,85,120,145,151,167],"most":[25],"popular":[26],"components":[27],"is":[31],"NIOS":[33,45,148,168],"II":[34,46,149,169],"processor.":[35],"As":[36],"well":[37],"as":[38,60,62,171],"ease":[39],"use":[41],"and":[42,57,92,110,117,143,163,184,191],"flexibility,":[43],"family":[47],"processors":[49],"offers":[50],"up":[51],"200":[53],"DMIPs":[54],"performance":[56,73,192],"can":[58,124],"cost":[59,131],"little":[61],"35":[63],"cents":[64],"worth":[65],"programmable":[67],"logic.":[68],"This":[69,154],"high":[70,128],"level":[71],"has":[74],"been":[75],"achieved":[76],"by":[77],"tailoring":[78],"processor":[80,170],"architecture":[81],"fully":[83],"exploit":[84],"resources":[87],"used.":[88],"Logic,":[89],"registers,":[90],"memory,":[91],"multipliers":[93],"have":[94,133,185],"different":[95],"relative":[96],"costs":[97],"when":[101],"compared":[102],"ASIC;":[105],"FPGA,":[108],"registers":[109],"memories":[111],"are":[112,176],"relatively":[113,127],"cheap,":[114],"whereas":[115],"logic":[116],"particular,":[119],"implementation":[121],"multiplexers":[123,162],"be":[125],"cost.":[129],"These":[130,174],"differences":[132],"influence":[135],"on":[136],"how":[137],"should":[139],"design":[140,146],"for":[141,160,178],"FPGAs,":[142],"defined":[144],"at":[150],"architectural":[152],"level.":[153],"paper":[155],"presents":[156],"some":[157],"novel":[158],"techniques":[159,175],"implementing":[161],"barrel-shifters":[164],"efficiently,":[165],"using":[166],"example.":[173],"useful":[177],"improving":[179],"designs":[181],"general,":[183],"typically":[186],"lead":[187],"area":[189],"reductions":[190],"improvements":[193],"20%.":[195]},"counts_by_year":[{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":2},{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
