{"id":"https://openalex.org/W2546953645","doi":"https://doi.org/10.1109/issoc.2003.1267737","title":"Design of a parametrizable low cost Ethernet MAC core for SoC solutions","display_name":"Design of a parametrizable low cost Ethernet MAC core for SoC solutions","publication_year":2004,"publication_date":"2004-06-21","ids":{"openalex":"https://openalex.org/W2546953645","doi":"https://doi.org/10.1109/issoc.2003.1267737","mag":"2546953645"},"language":"en","primary_location":{"id":"doi:10.1109/issoc.2003.1267737","is_oa":false,"landing_page_url":"https://doi.org/10.1109/issoc.2003.1267737","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings. 2003 International Symposium on System-on-Chip (IEEE Cat. No.03EX748)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5053182983","display_name":"Jose A. Moreno Zamora","orcid":"https://orcid.org/0000-0001-9197-9303"},"institutions":[{"id":"https://openalex.org/I80606768","display_name":"Universidad de Extremadura","ror":"https://ror.org/0174shg90","country_code":"ES","type":"education","lineage":["https://openalex.org/I80606768"]}],"countries":["ES"],"is_corresponding":true,"raw_author_name":"J.A. Moreno Zamora","raw_affiliation_strings":["Deparfment of Electronics, University of Extremadura, Badajoz, Spain"],"affiliations":[{"raw_affiliation_string":"Deparfment of Electronics, University of Extremadura, Badajoz, Spain","institution_ids":["https://openalex.org/I80606768"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5002483407","display_name":"P.J. Rodriguez Corrales","orcid":null},"institutions":[{"id":"https://openalex.org/I80606768","display_name":"Universidad de Extremadura","ror":"https://ror.org/0174shg90","country_code":"ES","type":"education","lineage":["https://openalex.org/I80606768"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"P.J. Rodriguez Corrales","raw_affiliation_strings":["School oflndustrial Engineering, University of Extremadura, Badajoz, Spain"],"affiliations":[{"raw_affiliation_string":"School oflndustrial Engineering, University of Extremadura, Badajoz, Spain","institution_ids":["https://openalex.org/I80606768"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5082308804","display_name":"J.M. Sanchez Perez","orcid":null},"institutions":[{"id":"https://openalex.org/I80606768","display_name":"Universidad de Extremadura","ror":"https://ror.org/0174shg90","country_code":"ES","type":"education","lineage":["https://openalex.org/I80606768"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"J.M. Sanchez Perez","raw_affiliation_strings":["Department ofhformatics, University of Extremadura, Caceres, Spain"],"affiliations":[{"raw_affiliation_string":"Department ofhformatics, University of Extremadura, Caceres, Spain","institution_ids":["https://openalex.org/I80606768"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5053182983"],"corresponding_institution_ids":["https://openalex.org/I80606768"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.30353647,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"139","last_page":"142"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9962000250816345,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9962000250816345,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9925000071525574,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12216","display_name":"Network Time Synchronization Technologies","score":0.9922000169754028,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/ethernet","display_name":"Ethernet","score":0.6739475727081299},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6215330362319946},{"id":"https://openalex.org/keywords/flexibility","display_name":"Flexibility (engineering)","score":0.5953347086906433},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.563206672668457},{"id":"https://openalex.org/keywords/implementation","display_name":"Implementation","score":0.5632005929946899},{"id":"https://openalex.org/keywords/industrial-ethernet","display_name":"Industrial Ethernet","score":0.5253913998603821},{"id":"https://openalex.org/keywords/carrier-ethernet","display_name":"Carrier Ethernet","score":0.5093463659286499},{"id":"https://openalex.org/keywords/core","display_name":"Core (optical fiber)","score":0.4872845411300659},{"id":"https://openalex.org/keywords/synchronous-ethernet","display_name":"Synchronous Ethernet","score":0.4853433668613434},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.47224897146224976},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.46947941184043884},{"id":"https://openalex.org/keywords/ethernet-over-sdh","display_name":"Ethernet over SDH","score":0.4457656145095825},{"id":"https://openalex.org/keywords/connection-oriented-ethernet","display_name":"Connection-oriented Ethernet","score":0.42672842741012573},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.35101553797721863},{"id":"https://openalex.org/keywords/ethernet-flow-control","display_name":"Ethernet flow control","score":0.3429335653781891},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.1650409698486328}],"concepts":[{"id":"https://openalex.org/C172173386","wikidata":"https://www.wikidata.org/wiki/Q79984","display_name":"Ethernet","level":2,"score":0.6739475727081299},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6215330362319946},{"id":"https://openalex.org/C2780598303","wikidata":"https://www.wikidata.org/wiki/Q65921492","display_name":"Flexibility (engineering)","level":2,"score":0.5953347086906433},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.563206672668457},{"id":"https://openalex.org/C26713055","wikidata":"https://www.wikidata.org/wiki/Q245962","display_name":"Implementation","level":2,"score":0.5632005929946899},{"id":"https://openalex.org/C167151114","wikidata":"https://www.wikidata.org/wiki/Q1661930","display_name":"Industrial Ethernet","level":3,"score":0.5253913998603821},{"id":"https://openalex.org/C151898751","wikidata":"https://www.wikidata.org/wiki/Q5046350","display_name":"Carrier Ethernet","level":3,"score":0.5093463659286499},{"id":"https://openalex.org/C2164484","wikidata":"https://www.wikidata.org/wiki/Q5170150","display_name":"Core (optical fiber)","level":2,"score":0.4872845411300659},{"id":"https://openalex.org/C205215620","wikidata":"https://www.wikidata.org/wiki/Q7662206","display_name":"Synchronous Ethernet","level":3,"score":0.4853433668613434},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.47224897146224976},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.46947941184043884},{"id":"https://openalex.org/C30188135","wikidata":"https://www.wikidata.org/wiki/Q1118613","display_name":"Ethernet over SDH","level":4,"score":0.4457656145095825},{"id":"https://openalex.org/C186844356","wikidata":"https://www.wikidata.org/wiki/Q5161679","display_name":"Connection-oriented Ethernet","level":4,"score":0.42672842741012573},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.35101553797721863},{"id":"https://openalex.org/C68178114","wikidata":"https://www.wikidata.org/wiki/Q5403359","display_name":"Ethernet flow control","level":3,"score":0.3429335653781891},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.1650409698486328},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/issoc.2003.1267737","is_oa":false,"landing_page_url":"https://doi.org/10.1109/issoc.2003.1267737","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings. 2003 International Symposium on System-on-Chip (IEEE Cat. No.03EX748)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","score":0.47999998927116394,"id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2383348237","https://openalex.org/W2356598257","https://openalex.org/W2489554667","https://openalex.org/W2375023940","https://openalex.org/W2356861538","https://openalex.org/W2156862550","https://openalex.org/W2375810997","https://openalex.org/W2155122972","https://openalex.org/W2357111730","https://openalex.org/W2525190005"],"abstract_inverted_index":{"This":[0],"paper":[1],"describes":[2],"an":[3],"efficient":[4],"Ethernet":[5,18],"medium":[6],"access":[7],"control":[8],"(MAC)":[9],"design,":[10],"according":[11],"to":[12],"IEEE":[13],"802.3":[14],"standards":[15],"for":[16,33,68,80],"fast":[17],"(100":[19],"Mbps)":[20,24],"a":[21,59,65,75],"10Base-T":[22],"(10":[23],"implementations":[25],"in":[26,40,58],"full":[27],"and":[28,46,72,74,78],"half":[29],"duplex":[30],"modes,":[31],"suitable":[32],"re-use":[34],"as":[35],"intellectual":[36],"property":[37],"(IP)":[38],"core":[39],"system-on-chip":[41],"(SoC)":[42],"designs.":[43],"The":[44],"description":[45],"contributed":[47],"results":[48],"exhibit":[49],"that":[50],"the":[51],"main":[52],"advantages":[53],"of":[54],"this":[55],"design":[56],"reside":[57],"really":[60],"low":[61],"logic":[62],"cost":[63],"keeping":[64],"great":[66],"tolerance":[67],"external":[69],"clock":[70],"frequencies":[71],"domains,":[73],"high":[76],"configurability":[77],"flexibility":[79],"master":[81],"processors":[82],"interface.":[83]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}