{"id":"https://openalex.org/W2538379351","doi":"https://doi.org/10.1109/issoc.2003.1267723","title":"A highly efficient modeling style for heterogeneous bus architectures","display_name":"A highly efficient modeling style for heterogeneous bus architectures","publication_year":2004,"publication_date":"2004-06-21","ids":{"openalex":"https://openalex.org/W2538379351","doi":"https://doi.org/10.1109/issoc.2003.1267723","mag":"2538379351"},"language":"en","primary_location":{"id":"doi:10.1109/issoc.2003.1267723","is_oa":false,"landing_page_url":"https://doi.org/10.1109/issoc.2003.1267723","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings. 2003 International Symposium on System-on-Chip (IEEE Cat. No.03EX748)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5049434837","display_name":"M. Ariyamparambath","orcid":null},"institutions":[{"id":"https://openalex.org/I4210088951","display_name":"Synopsys (United States)","ror":"https://ror.org/013by2m91","country_code":"US","type":"company","lineage":["https://openalex.org/I4210088951"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"M. Ariyamparambath","raw_affiliation_strings":["Solutions Group, Synopsys, Inc., USA"],"affiliations":[{"raw_affiliation_string":"Solutions Group, Synopsys, Inc., USA","institution_ids":["https://openalex.org/I4210088951"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5007496061","display_name":"D. Bussaglia","orcid":null},"institutions":[{"id":"https://openalex.org/I4210088951","display_name":"Synopsys (United States)","ror":"https://ror.org/013by2m91","country_code":"US","type":"company","lineage":["https://openalex.org/I4210088951"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"D. Bussaglia","raw_affiliation_strings":["Solutions Group, Synopsys, Inc., USA"],"affiliations":[{"raw_affiliation_string":"Solutions Group, Synopsys, Inc., USA","institution_ids":["https://openalex.org/I4210088951"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5037215361","display_name":"B. Reinkemeier","orcid":null},"institutions":[{"id":"https://openalex.org/I4210088951","display_name":"Synopsys (United States)","ror":"https://ror.org/013by2m91","country_code":"US","type":"company","lineage":["https://openalex.org/I4210088951"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"B. Reinkemeier","raw_affiliation_strings":["Solutions Group, Synopsys, Inc., USA"],"affiliations":[{"raw_affiliation_string":"Solutions Group, Synopsys, Inc., USA","institution_ids":["https://openalex.org/I4210088951"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5074500359","display_name":"Tim Kogel","orcid":"https://orcid.org/0000-0002-7397-2615"},"institutions":[{"id":"https://openalex.org/I887968799","display_name":"RWTH Aachen University","ror":"https://ror.org/04xfq0f34","country_code":"DE","type":"education","lineage":["https://openalex.org/I887968799"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"T. Kogel","raw_affiliation_strings":["Integrated Signal Processing Systems, RWTH Aachen University of Technology, Aachen, Germany"],"affiliations":[{"raw_affiliation_string":"Integrated Signal Processing Systems, RWTH Aachen University of Technology, Aachen, Germany","institution_ids":["https://openalex.org/I887968799"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5041183775","display_name":"Torsten Kempf","orcid":null},"institutions":[{"id":"https://openalex.org/I887968799","display_name":"RWTH Aachen University","ror":"https://ror.org/04xfq0f34","country_code":"DE","type":"education","lineage":["https://openalex.org/I887968799"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"T. Kempf","raw_affiliation_strings":["Integrated Signal Processing Systems, RWTH Aachen University of Technology, Aachen, Germany"],"affiliations":[{"raw_affiliation_string":"Integrated Signal Processing Systems, RWTH Aachen University of Technology, Aachen, Germany","institution_ids":["https://openalex.org/I887968799"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5049434837"],"corresponding_institution_ids":["https://openalex.org/I4210088951"],"apc_list":null,"apc_paid":null,"fwci":0.7472,"has_fulltext":false,"cited_by_count":10,"citation_normalized_percentile":{"value":0.79781526,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"83","last_page":"87"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8323262929916382},{"id":"https://openalex.org/keywords/executable","display_name":"Executable","score":0.7816851139068604},{"id":"https://openalex.org/keywords/abstraction","display_name":"Abstraction","score":0.5938781499862671},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5758346915245056},{"id":"https://openalex.org/keywords/router","display_name":"Router","score":0.5467092990875244},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5178473591804504},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.5063327550888062},{"id":"https://openalex.org/keywords/electronic-system-level-design-and-verification","display_name":"Electronic system-level design and verification","score":0.4818214476108551},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.4765101969242096},{"id":"https://openalex.org/keywords/abstraction-layer","display_name":"Abstraction layer","score":0.4678170382976532},{"id":"https://openalex.org/keywords/systemc","display_name":"SystemC","score":0.43748411536216736},{"id":"https://openalex.org/keywords/system-bus","display_name":"System bus","score":0.42831605672836304},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.3432290852069855},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.1701837182044983},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.16409963369369507},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.13395431637763977},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.12550795078277588}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8323262929916382},{"id":"https://openalex.org/C160145156","wikidata":"https://www.wikidata.org/wiki/Q778586","display_name":"Executable","level":2,"score":0.7816851139068604},{"id":"https://openalex.org/C124304363","wikidata":"https://www.wikidata.org/wiki/Q673661","display_name":"Abstraction","level":2,"score":0.5938781499862671},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5758346915245056},{"id":"https://openalex.org/C2775896111","wikidata":"https://www.wikidata.org/wiki/Q642560","display_name":"Router","level":2,"score":0.5467092990875244},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5178473591804504},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.5063327550888062},{"id":"https://openalex.org/C77495112","wikidata":"https://www.wikidata.org/wiki/Q5358436","display_name":"Electronic system-level design and verification","level":2,"score":0.4818214476108551},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.4765101969242096},{"id":"https://openalex.org/C147358964","wikidata":"https://www.wikidata.org/wiki/Q1200992","display_name":"Abstraction layer","level":3,"score":0.4678170382976532},{"id":"https://openalex.org/C2776928060","wikidata":"https://www.wikidata.org/wiki/Q1753563","display_name":"SystemC","level":2,"score":0.43748411536216736},{"id":"https://openalex.org/C136321198","wikidata":"https://www.wikidata.org/wiki/Q2377054","display_name":"System bus","level":2,"score":0.42831605672836304},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.3432290852069855},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.1701837182044983},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.16409963369369507},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.13395431637763977},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.12550795078277588},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C111472728","wikidata":"https://www.wikidata.org/wiki/Q9471","display_name":"Epistemology","level":1,"score":0.0},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/issoc.2003.1267723","is_oa":false,"landing_page_url":"https://doi.org/10.1109/issoc.2003.1267723","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings. 2003 International Symposium on System-on-Chip (IEEE Cat. No.03EX748)","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.69.3521","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.69.3521","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.iss.rwth-aachen.de/4_publikationen/res_pdf/2003manojSOCO_busses.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.47999998927116394,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W1573419743","https://openalex.org/W2043918852","https://openalex.org/W2061341864","https://openalex.org/W2119677480","https://openalex.org/W2122962786","https://openalex.org/W2148740615","https://openalex.org/W2157357797","https://openalex.org/W4205317033","https://openalex.org/W4235366349","https://openalex.org/W4238490149","https://openalex.org/W6817076167"],"related_works":["https://openalex.org/W2052474397","https://openalex.org/W2790192245","https://openalex.org/W4256575154","https://openalex.org/W1525398417","https://openalex.org/W1831349210","https://openalex.org/W2121502652","https://openalex.org/W2552808814","https://openalex.org/W2143185107","https://openalex.org/W2101005401","https://openalex.org/W4248763817"],"abstract_inverted_index":{"The":[0,20,103,133],"ever":[1],"increasing":[2],"complexity":[3],"and":[4,99,112,124],"heterogeneity":[5],"of":[6,12,55,62,83,121,126,161],"modern":[7],"systems-on-chip":[8],"designs":[9],"demands":[10],"validation":[11,120],"the":[13,30,43,91,106,110,119,122,127,141,145,149],"system":[14,92,128],"performance":[15,78,125],"as":[16,18],"early":[17],"possible.":[19],"on-chip":[21,36],"bus":[22,37,57,67,74],"architectures":[23,38,58,68],"play":[24],"an":[25,51,156],"important":[26],"role":[27],"to":[28,41,148],"meet":[29],"design":[31,44,163],"performance.":[32],"Today":[33],"many":[34],"heterogeneous":[35,56],"are":[39],"defined":[40],"address":[42],"exploration.":[45],"In":[46],"this":[47],"paper":[48],"we":[49],"introduce":[50],"efficient":[52,111],"modeling":[53,86],"style":[54,87],"at":[59,129,144],"high":[60,130],"levels":[61],"abstraction.":[63],"We":[64],"capture":[65],"different":[66],"by":[69],"using":[70],"a":[71,95],"generic,":[72],"parametrizable":[73],"model,":[75],"which":[76,115],"captures":[77],"issues":[79],"without":[80],"significant":[81],"loss":[82],"accuracy.":[84],"Our":[85],"is":[88],"based":[89],"on":[90],"C":[93],"language,":[94],"special":[96],"channel":[97],"library":[98],"attached":[100],"coding":[101],"style.":[102],"combination":[104],"provides":[105],"ground":[107],"layer":[108],"for":[109,155],"fast":[113],"simulation,":[114],"in":[116],"turn":[117],"enables":[118],"functionality":[123],"abstraction":[131],"levels.":[132],"approach":[134],"has":[135],"been":[136],"successfully":[137],"used":[138],"from":[139],"defining":[140],"executable":[142],"specification":[143],"functional":[146],"level":[147],"architecture":[150],"explorations":[151],"with":[152,159],"HW/SW":[153],"integration":[154],"IPv4":[157],"router":[158],"quality":[160],"support,":[162],"example.":[164]},"counts_by_year":[{"year":2017,"cited_by_count":1},{"year":2012,"cited_by_count":2}],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}