{"id":"https://openalex.org/W2542473914","doi":"https://doi.org/10.1109/issoc.2003.1267707","title":"COFFEE - a core for free","display_name":"COFFEE - a core for free","publication_year":2004,"publication_date":"2004-06-21","ids":{"openalex":"https://openalex.org/W2542473914","doi":"https://doi.org/10.1109/issoc.2003.1267707","mag":"2542473914"},"language":"en","primary_location":{"id":"doi:10.1109/issoc.2003.1267707","is_oa":false,"landing_page_url":"https://doi.org/10.1109/issoc.2003.1267707","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings. 2003 International Symposium on System-on-Chip (IEEE Cat. No.03EX748)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5090403321","display_name":"J. Kylliainen","orcid":null},"institutions":[{"id":"https://openalex.org/I166825849","display_name":"Tampere University","ror":"https://ror.org/033003e23","country_code":"FI","type":"education","lineage":["https://openalex.org/I166825849"]},{"id":"https://openalex.org/I4210133110","display_name":"Tampere University","ror":null,"country_code":"FI","type":null,"lineage":["https://openalex.org/I4210133110"]}],"countries":["FI"],"is_corresponding":true,"raw_author_name":"J. Kylliainen","raw_affiliation_strings":["Tampere University of Technology, Finland"],"affiliations":[{"raw_affiliation_string":"Tampere University of Technology, Finland","institution_ids":["https://openalex.org/I166825849","https://openalex.org/I4210133110"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5035297149","display_name":"Jari Nurmi","orcid":"https://orcid.org/0000-0003-2169-4606"},"institutions":[{"id":"https://openalex.org/I166825849","display_name":"Tampere University","ror":"https://ror.org/033003e23","country_code":"FI","type":"education","lineage":["https://openalex.org/I166825849"]},{"id":"https://openalex.org/I4210133110","display_name":"Tampere University","ror":null,"country_code":"FI","type":null,"lineage":["https://openalex.org/I4210133110"]}],"countries":["FI"],"is_corresponding":false,"raw_author_name":"J. Nurmi","raw_affiliation_strings":["Tampere University of Technology, Finland"],"affiliations":[{"raw_affiliation_string":"Tampere University of Technology, Finland","institution_ids":["https://openalex.org/I166825849","https://openalex.org/I4210133110"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5088673260","display_name":"M. Kuulusa","orcid":null},"institutions":[{"id":"https://openalex.org/I166825849","display_name":"Tampere University","ror":"https://ror.org/033003e23","country_code":"FI","type":"education","lineage":["https://openalex.org/I166825849"]},{"id":"https://openalex.org/I4210133110","display_name":"Tampere University","ror":null,"country_code":"FI","type":null,"lineage":["https://openalex.org/I4210133110"]}],"countries":["FI"],"is_corresponding":false,"raw_author_name":"M. Kuulusa","raw_affiliation_strings":["Tampere University of Technology, Finland"],"affiliations":[{"raw_affiliation_string":"Tampere University of Technology, Finland","institution_ids":["https://openalex.org/I166825849","https://openalex.org/I4210133110"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5090403321"],"corresponding_institution_ids":["https://openalex.org/I166825849","https://openalex.org/I4210133110"],"apc_list":null,"apc_paid":null,"fwci":3.1597,"has_fulltext":false,"cited_by_count":28,"citation_normalized_percentile":{"value":0.91778677,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"17","last_page":"22"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9979000091552734,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9979000091552734,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9939000010490417,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.972000002861023,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/reduced-instruction-set-computing","display_name":"Reduced instruction set computing","score":0.7645632028579712},{"id":"https://openalex.org/keywords/core","display_name":"Core (optical fiber)","score":0.7197182774543762},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7000830173492432},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.612982988357544},{"id":"https://openalex.org/keywords/processor-design","display_name":"Processor design","score":0.5672182440757751},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.544935941696167},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.5332013964653015},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.5197181701660156},{"id":"https://openalex.org/keywords/many-core","display_name":"Many core","score":0.49288344383239746},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.47964245080947876},{"id":"https://openalex.org/keywords/microarchitecture","display_name":"Microarchitecture","score":0.45756417512893677},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.35190027952194214},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.25541403889656067},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.17427781224250793}],"concepts":[{"id":"https://openalex.org/C126298526","wikidata":"https://www.wikidata.org/wiki/Q189376","display_name":"Reduced instruction set computing","level":3,"score":0.7645632028579712},{"id":"https://openalex.org/C2164484","wikidata":"https://www.wikidata.org/wiki/Q5170150","display_name":"Core (optical fiber)","level":2,"score":0.7197182774543762},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7000830173492432},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.612982988357544},{"id":"https://openalex.org/C526435321","wikidata":"https://www.wikidata.org/wiki/Q1303814","display_name":"Processor design","level":2,"score":0.5672182440757751},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.544935941696167},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.5332013964653015},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.5197181701660156},{"id":"https://openalex.org/C3020431745","wikidata":"https://www.wikidata.org/wiki/Q25325220","display_name":"Many core","level":2,"score":0.49288344383239746},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.47964245080947876},{"id":"https://openalex.org/C107598950","wikidata":"https://www.wikidata.org/wiki/Q259864","display_name":"Microarchitecture","level":2,"score":0.45756417512893677},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.35190027952194214},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.25541403889656067},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.17427781224250793},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/issoc.2003.1267707","is_oa":false,"landing_page_url":"https://doi.org/10.1109/issoc.2003.1267707","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings. 2003 International Symposium on System-on-Chip (IEEE Cat. No.03EX748)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","score":0.5299999713897705,"id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":4,"referenced_works":["https://openalex.org/W1581210787","https://openalex.org/W1986698883","https://openalex.org/W2341873030","https://openalex.org/W3145830094"],"related_works":["https://openalex.org/W2993622674","https://openalex.org/W2534569838","https://openalex.org/W182515070","https://openalex.org/W4367172762","https://openalex.org/W4310584696","https://openalex.org/W2164026451","https://openalex.org/W4364295250","https://openalex.org/W3173973232","https://openalex.org/W3116750762","https://openalex.org/W2036206036"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"design":[3,20,33],"and":[4,28],"implementation":[5],"of":[6,16,22,30,39],"an":[7],"open":[8],"source":[9],"processor":[10,42],"core":[11,25],"developed":[12,41],"at":[13],"Tampere":[14],"University":[15],"Technology,":[17],"Finland.":[18],"The":[19,37],"guidelines":[21],"a":[23],"RISC":[24,45],"are":[26,35],"introduced":[27],"some":[29],"the":[31,40],"typical":[32],"tradeoffs":[34],"presented.":[36],"architecture":[38],"engine,":[43],"COFFEE":[44],"core,":[46],"is":[47],"explained.":[48]},"counts_by_year":[{"year":2016,"cited_by_count":2},{"year":2015,"cited_by_count":2},{"year":2013,"cited_by_count":5},{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}