{"id":"https://openalex.org/W2536080827","doi":"https://doi.org/10.1109/issoc.2003.1267704","title":"SoC integration of programmable cores","display_name":"SoC integration of programmable cores","publication_year":2004,"publication_date":"2004-06-21","ids":{"openalex":"https://openalex.org/W2536080827","doi":"https://doi.org/10.1109/issoc.2003.1267704","mag":"2536080827"},"language":"en","primary_location":{"id":"doi:10.1109/issoc.2003.1267704","is_oa":false,"landing_page_url":"https://doi.org/10.1109/issoc.2003.1267704","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings. 2003 International Symposium on System-on-Chip (IEEE Cat. No.03EX748)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5083999820","display_name":"Andreas Hoffmann","orcid":"https://orcid.org/0000-0001-8669-3087"},"institutions":[{"id":"https://openalex.org/I4210146450","display_name":"AtlantiCare","ror":"https://ror.org/03vdj0f87","country_code":"US","type":"healthcare","lineage":["https://openalex.org/I4210146450"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"A. Hoffmann","raw_affiliation_strings":["CoWare, Inc., USA"],"affiliations":[{"raw_affiliation_string":"CoWare, Inc., USA","institution_ids":["https://openalex.org/I4210146450"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5053671404","display_name":"Robert Langridge","orcid":"https://orcid.org/0000-0002-5092-0468"},"institutions":[{"id":"https://openalex.org/I4210146450","display_name":"AtlantiCare","ror":"https://ror.org/03vdj0f87","country_code":"US","type":"healthcare","lineage":["https://openalex.org/I4210146450"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"R. Langridge","raw_affiliation_strings":["CoWare, Inc., USA"],"affiliations":[{"raw_affiliation_string":"CoWare, Inc., USA","institution_ids":["https://openalex.org/I4210146450"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5091787111","display_name":"D. Machin","orcid":null},"institutions":[{"id":"https://openalex.org/I4210146450","display_name":"AtlantiCare","ror":"https://ror.org/03vdj0f87","country_code":"US","type":"healthcare","lineage":["https://openalex.org/I4210146450"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"D. Machin","raw_affiliation_strings":["CoWare, Inc., USA"],"affiliations":[{"raw_affiliation_string":"CoWare, Inc., USA","institution_ids":["https://openalex.org/I4210146450"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5083999820"],"corresponding_institution_ids":["https://openalex.org/I4210146450"],"apc_list":null,"apc_paid":null,"fwci":0.2317,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.67236796,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"11","last_page":"11"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9961000084877014,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/systemc","display_name":"SystemC","score":0.9470305442810059},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8298985958099365},{"id":"https://openalex.org/keywords/bottleneck","display_name":"Bottleneck","score":0.6796269416809082},{"id":"https://openalex.org/keywords/transaction-level-modeling","display_name":"Transaction-level modeling","score":0.5993614792823792},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5355263948440552},{"id":"https://openalex.org/keywords/concurrency","display_name":"Concurrency","score":0.4758588671684265},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4754043519496918},{"id":"https://openalex.org/keywords/interface","display_name":"Interface (matter)","score":0.4708383083343506},{"id":"https://openalex.org/keywords/register-transfer-level","display_name":"Register-transfer level","score":0.4461911618709564},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.43357789516448975},{"id":"https://openalex.org/keywords/electronic-system-level-design-and-verification","display_name":"Electronic system-level design and verification","score":0.4213572144508362},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.41224128007888794},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.3604976236820221},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.293861448764801},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.29243722558021545},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.2630281448364258},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.11325937509536743}],"concepts":[{"id":"https://openalex.org/C2776928060","wikidata":"https://www.wikidata.org/wiki/Q1753563","display_name":"SystemC","level":2,"score":0.9470305442810059},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8298985958099365},{"id":"https://openalex.org/C2780513914","wikidata":"https://www.wikidata.org/wiki/Q18210350","display_name":"Bottleneck","level":2,"score":0.6796269416809082},{"id":"https://openalex.org/C169571997","wikidata":"https://www.wikidata.org/wiki/Q966099","display_name":"Transaction-level modeling","level":3,"score":0.5993614792823792},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5355263948440552},{"id":"https://openalex.org/C193702766","wikidata":"https://www.wikidata.org/wiki/Q1414548","display_name":"Concurrency","level":2,"score":0.4758588671684265},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4754043519496918},{"id":"https://openalex.org/C113843644","wikidata":"https://www.wikidata.org/wiki/Q901882","display_name":"Interface (matter)","level":4,"score":0.4708383083343506},{"id":"https://openalex.org/C34854456","wikidata":"https://www.wikidata.org/wiki/Q1484552","display_name":"Register-transfer level","level":4,"score":0.4461911618709564},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.43357789516448975},{"id":"https://openalex.org/C77495112","wikidata":"https://www.wikidata.org/wiki/Q5358436","display_name":"Electronic system-level design and verification","level":2,"score":0.4213572144508362},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.41224128007888794},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.3604976236820221},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.293861448764801},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.29243722558021545},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.2630281448364258},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.11325937509536743},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.0},{"id":"https://openalex.org/C157915830","wikidata":"https://www.wikidata.org/wiki/Q2928001","display_name":"Bubble","level":2,"score":0.0},{"id":"https://openalex.org/C129307140","wikidata":"https://www.wikidata.org/wiki/Q6795880","display_name":"Maximum bubble pressure method","level":3,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/issoc.2003.1267704","is_oa":false,"landing_page_url":"https://doi.org/10.1109/issoc.2003.1267704","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings. 2003 International Symposium on System-on-Chip (IEEE Cat. No.03EX748)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.6299999952316284,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W1525398417","https://openalex.org/W2532163536","https://openalex.org/W2035296141","https://openalex.org/W4247397443","https://openalex.org/W1831349210","https://openalex.org/W2548514518","https://openalex.org/W3206586607","https://openalex.org/W2133642747","https://openalex.org/W1603163876","https://openalex.org/W2156420848"],"abstract_inverted_index":{"SystemC":[0,35,88],"is":[1,57,76,102,148],"considered":[2],"as":[3],"the":[4,14,31,65,79,91,97,134,152,164],"emerging":[5],"industry":[6],"standard":[7],"for":[8,110,160],"system":[9,165],"architecture":[10],"design,":[11,63],"because":[12],"on":[13],"one":[15],"hand":[16,33],"side":[17],"being":[18],"a":[19,142,157],"native":[20],"C++":[21],"library":[22],"it":[23],"fits":[24],"well":[25],"into":[26],"any":[27],"SW":[28],"flow.":[29],"On":[30],"other":[32],"side,":[34],"incorporates":[36],"mandatory":[37],"HW":[38],"semantics":[39],"like":[40,114],"concurrency,":[41],"module":[42],"hierarchy,":[43],"and":[44,73,154],"explicit":[45],"timing":[46],"to":[47,60,121,150],"create":[48],"architectural":[49,161],"models.":[50],"However,":[51],"having":[52],"an":[53],"expressive":[54],"language":[55],"alone":[56],"not":[58],"sufficient":[59],"enable":[61],"system-level":[62],"instead":[64],"major":[66],"bottleneck":[67],"in":[68,124,141],"terms":[69],"of":[70,136,156],"simulation":[71,125],"speed":[72],"modelling":[74,85,93,145],"efficiency":[75,126],"caused":[77],"by":[78,104],"highly":[80],"detailed":[81],"register-transfer":[82],"level":[83],"(RTL)":[84],"style.":[86],"Therefore,":[87],"2.0":[89],"advocates":[90],"transaction-level":[92],"(TLM)":[94],"paradigm,":[95],"where":[96],"pin-accurate":[98],"communication":[99],"between":[100],"modules":[101],"replaced":[103],"condensed":[105,144],"interface":[106],"method":[107],"calls.":[108],"Especially":[109],"complex":[111],"bus":[112],"protocols":[113],"AMBA":[115],"AHB,":[116],"this":[117],"simplification":[118],"attains":[119],"up":[120],"two":[122],"orders":[123],"without":[127],"sacrificing":[128],"cycle":[129],"accuracy.":[130],"TLM":[131],"along":[132],"with":[133],"concept":[135],"dynamic":[137],"sensitivity":[138],"also":[139],"results":[140],"very":[143],"style,":[146],"which":[147],"essential":[149],"motivate":[151],"creation":[153],"maintenance":[155],"separate":[158],"model":[159],"exploration":[162],"at":[163],"level.":[166]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}