{"id":"https://openalex.org/W7133332866","doi":"https://doi.org/10.1109/isscc49663.2026.11409351","title":"17.1 NVIDIA GB10: SoC Built for AI Acceleration","display_name":"17.1 NVIDIA GB10: SoC Built for AI Acceleration","publication_year":2026,"publication_date":"2026-02-15","ids":{"openalex":"https://openalex.org/W7133332866","doi":"https://doi.org/10.1109/isscc49663.2026.11409351"},"language":null,"primary_location":{"id":"doi:10.1109/isscc49663.2026.11409351","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isscc49663.2026.11409351","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2026 IEEE International Solid-State Circuits Conference (ISSCC)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5085194808","display_name":"Andi Skende","orcid":null},"institutions":[{"id":"https://openalex.org/I1304085615","display_name":"Nvidia (United Kingdom)","ror":"https://ror.org/02kr42612","country_code":"GB","type":"company","lineage":["https://openalex.org/I1304085615","https://openalex.org/I4210127875"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"A. Skende","raw_affiliation_strings":["Nvidia,Westford,MA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Nvidia,Westford,MA","institution_ids":["https://openalex.org/I1304085615"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5127957761","display_name":"G. Rosseel","orcid":null},"institutions":[{"id":"https://openalex.org/I4210127875","display_name":"Nvidia (United States)","ror":"https://ror.org/03jdj4y14","country_code":"US","type":"company","lineage":["https://openalex.org/I4210127875"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"G. Rosseel","raw_affiliation_strings":["Nvidia,Santa Clara,CA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Nvidia,Santa Clara,CA","institution_ids":["https://openalex.org/I4210127875"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5050270997","display_name":"Nathaniel Pinckney","orcid":"https://orcid.org/0000-0001-6159-8964"},"institutions":[{"id":"https://openalex.org/I1304085615","display_name":"Nvidia (United Kingdom)","ror":"https://ror.org/02kr42612","country_code":"GB","type":"company","lineage":["https://openalex.org/I1304085615","https://openalex.org/I4210127875"]},{"id":"https://openalex.org/I4210127875","display_name":"Nvidia (United States)","ror":"https://ror.org/03jdj4y14","country_code":"US","type":"company","lineage":["https://openalex.org/I4210127875"]}],"countries":["GB","US"],"is_corresponding":false,"raw_author_name":"N. Pinckney","raw_affiliation_strings":["Nvidia,Austin,TX"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Nvidia,Austin,TX","institution_ids":["https://openalex.org/I1304085615","https://openalex.org/I4210127875"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.13408578,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"298","last_page":"300"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.18150000274181366,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.18150000274181366,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.125,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.07490000128746033,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/acceleration","display_name":"Acceleration","score":0.6079999804496765},{"id":"https://openalex.org/keywords/spark","display_name":"SPARK (programming language)","score":0.503000020980835},{"id":"https://openalex.org/keywords/central-processing-unit","display_name":"Central processing unit","score":0.32839998602867126},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.3140000104904175},{"id":"https://openalex.org/keywords/interface","display_name":"Interface (matter)","score":0.28769999742507935},{"id":"https://openalex.org/keywords/tensor","display_name":"Tensor (intrinsic definition)","score":0.2865999937057495}],"concepts":[{"id":"https://openalex.org/C117896860","wikidata":"https://www.wikidata.org/wiki/Q11376","display_name":"Acceleration","level":2,"score":0.6079999804496765},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6062999963760376},{"id":"https://openalex.org/C2781215313","wikidata":"https://www.wikidata.org/wiki/Q3493345","display_name":"SPARK (programming language)","level":2,"score":0.503000020980835},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.41850000619888306},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3856000006198883},{"id":"https://openalex.org/C121684516","wikidata":"https://www.wikidata.org/wiki/Q7600677","display_name":"Computer graphics (images)","level":1,"score":0.3684000074863434},{"id":"https://openalex.org/C459310","wikidata":"https://www.wikidata.org/wiki/Q117801","display_name":"Computational science","level":1,"score":0.3677000105381012},{"id":"https://openalex.org/C49154492","wikidata":"https://www.wikidata.org/wiki/Q5300","display_name":"Central processing unit","level":2,"score":0.32839998602867126},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.3140000104904175},{"id":"https://openalex.org/C113843644","wikidata":"https://www.wikidata.org/wiki/Q901882","display_name":"Interface (matter)","level":4,"score":0.28769999742507935},{"id":"https://openalex.org/C155281189","wikidata":"https://www.wikidata.org/wiki/Q3518150","display_name":"Tensor (intrinsic definition)","level":2,"score":0.2865999937057495},{"id":"https://openalex.org/C111106434","wikidata":"https://www.wikidata.org/wiki/Q1072430","display_name":"Die (integrated circuit)","level":2,"score":0.2797999978065491},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2768999934196472},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.2736000120639801},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.2646999955177307},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.2542000114917755},{"id":"https://openalex.org/C2986737658","wikidata":"https://www.wikidata.org/wiki/Q30103009","display_name":"Tensor decomposition","level":3,"score":0.25040000677108765}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isscc49663.2026.11409351","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isscc49663.2026.11409351","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2026 IEEE International Solid-State Circuits Conference (ISSCC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.8299642205238342}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":[],"abstract_inverted_index":{"This":[0],"paper":[1],"details":[2],"the":[3,8],"GB10":[4],"SoC":[5],"that":[6],"powers":[7],"recently":[9],"launched":[10],"DGXTM":[11],"Spark":[12],"workstation.":[13],"A":[14],"dual-die":[15],"solution,":[16],"fabricated":[17],"in":[18],"TSMC's":[19],"3":[20],"nm":[21],"process,":[22],"co-packages":[23],"a":[24,33],"CPU":[25],"die":[26,36],"featuring":[27],"20":[28],"ARM":[29],"v9.2":[30],"cores":[31],"alongside":[32],"Blackwell":[34],"iGPU":[35],"tuned":[37],"for":[38],"desktop":[39],"performance.":[40],"The":[41],"GPU":[42],"features":[43],"5th-generation":[44],"Tensor":[45],"Cores,":[46],"4th-generation":[47],"RT":[48],"cores,":[49],"and":[50,59],"24MB":[51],"of":[52,57,61],"L2":[53],"cache,":[54],"achieving":[55],"31TFLOPS":[56],"FP32":[58],"1PFLOPS":[60],"FP4.":[62]},"counts_by_year":[],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2026-03-04T00:00:00"}
