{"id":"https://openalex.org/W7133320110","doi":"https://doi.org/10.1109/isscc49663.2026.11409347","title":"10.6 A Hybrid-Bonded 12.1Tops/mm <sup>2</sup> 5 6-Core DNN Processor with 2.5Tb/s/mm <sup>2</sup> 3D Network on Chip","display_name":"10.6 A Hybrid-Bonded 12.1Tops/mm <sup>2</sup> 5 6-Core DNN Processor with 2.5Tb/s/mm <sup>2</sup> 3D Network on Chip","publication_year":2026,"publication_date":"2026-02-15","ids":{"openalex":"https://openalex.org/W7133320110","doi":"https://doi.org/10.1109/isscc49663.2026.11409347"},"language":null,"primary_location":{"id":"doi:10.1109/isscc49663.2026.11409347","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isscc49663.2026.11409347","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2026 IEEE International Solid-State Circuits Conference (ISSCC)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5030456056","display_name":"Phil Knag","orcid":"https://orcid.org/0000-0001-6794-8806"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Phil C. Knag","raw_affiliation_strings":["Intel,Hillsboro,OR"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel,Hillsboro,OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5014493157","display_name":"Gregory K. Chen","orcid":"https://orcid.org/0000-0002-4813-3844"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Gregory K. Chen","raw_affiliation_strings":["Intel,Hillsboro,OR"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel,Hillsboro,OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5031054921","display_name":"Shanshan Xie","orcid":"https://orcid.org/0000-0001-8411-3050"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Shanshan Xie","raw_affiliation_strings":["Intel,Austin,TX"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel,Austin,TX","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5024748519","display_name":"Satish Yada","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Satish Yada","raw_affiliation_strings":["Intel,Hillsboro,OR"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel,Hillsboro,OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5061984123","display_name":"Wei Xiang Wu","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Wei Wu","raw_affiliation_strings":["Intel,Hillsboro,OR"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel,Hillsboro,OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5127945455","display_name":"Yu-Shiang Lin","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Yu-Shiang Lin","raw_affiliation_strings":["Intel,Hillsboro,OR"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel,Hillsboro,OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5128033481","display_name":"Alexander Kashirin","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Alexander Kashirin","raw_affiliation_strings":["Intel,Hillsboro,OR"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel,Hillsboro,OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5076758244","display_name":"Xiemei Meng","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Xiemei Meng","raw_affiliation_strings":["Intel,Austin,TX"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel,Austin,TX","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5019872849","display_name":"R. Criss","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Russell Criss","raw_affiliation_strings":["Intel,Hillsboro,OR"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel,Hillsboro,OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5077447335","display_name":"Ana Sonia Leon","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ana Sonia Leon","raw_affiliation_strings":["Intel,Santa Clara,CA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel,Santa Clara,CA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5112838079","display_name":"Carlos Tokunaga","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Carlos Tokunaga","raw_affiliation_strings":["Intel,Hillsboro,OR"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel,Hillsboro,OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5074107306","display_name":"Ram Krishnamurthy","orcid":"https://orcid.org/0000-0002-2428-7099"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ram K. Krishnamurthy","raw_affiliation_strings":["Intel,Hillsboro,OR"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel,Hillsboro,OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5067753561","display_name":"James Tschanz","orcid":"https://orcid.org/0000-0003-0317-4332"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"James W. Tschanz","raw_affiliation_strings":["Intel,Hillsboro,OR"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel,Hillsboro,OR","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I1343180700"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.14115548,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"178","last_page":"180"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.8499000072479248,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.8499000072479248,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11661","display_name":"Copper Interconnects and Reliability","score":0.02759999968111515,"subfield":{"id":"https://openalex.org/subfields/2504","display_name":"Electronic, Optical and Magnetic Materials"},"field":{"id":"https://openalex.org/fields/25","display_name":"Materials Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.016499999910593033,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.5554999709129333},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.5230000019073486},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.5085999965667725},{"id":"https://openalex.org/keywords/memory-bandwidth","display_name":"Memory bandwidth","score":0.49889999628067017},{"id":"https://openalex.org/keywords/bandwidth","display_name":"Bandwidth (computing)","score":0.490200012922287},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.46000000834465027},{"id":"https://openalex.org/keywords/artificial-neural-network","display_name":"Artificial neural network","score":0.4293000102043152},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.4212000072002411}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7303000092506409},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.5554999709129333},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.5230000019073486},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.5085999965667725},{"id":"https://openalex.org/C188045654","wikidata":"https://www.wikidata.org/wiki/Q17148339","display_name":"Memory bandwidth","level":2,"score":0.49889999628067017},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.490200012922287},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.46000000834465027},{"id":"https://openalex.org/C50644808","wikidata":"https://www.wikidata.org/wiki/Q192776","display_name":"Artificial neural network","level":2,"score":0.4293000102043152},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.4212000072002411},{"id":"https://openalex.org/C2775941181","wikidata":"https://www.wikidata.org/wiki/Q861004","display_name":"Image processor","level":4,"score":0.42100000381469727},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4203999936580658},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4090000092983246},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3774000108242035},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.37049999833106995},{"id":"https://openalex.org/C74366991","wikidata":"https://www.wikidata.org/wiki/Q2755335","display_name":"Network processor","level":3,"score":0.3465000092983246},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.3253999948501587},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.2955999970436096},{"id":"https://openalex.org/C161824985","wikidata":"https://www.wikidata.org/wiki/Q919509","display_name":"Vector processor","level":2,"score":0.2736000120639801},{"id":"https://openalex.org/C2994168587","wikidata":"https://www.wikidata.org/wiki/Q5295","display_name":"Random access memory","level":2,"score":0.2581999897956848},{"id":"https://openalex.org/C9417928","wikidata":"https://www.wikidata.org/wiki/Q1070689","display_name":"Image processing","level":3,"score":0.25459998846054077},{"id":"https://openalex.org/C128519102","wikidata":"https://www.wikidata.org/wiki/Q339554","display_name":"Network on a chip","level":2,"score":0.2515999972820282}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isscc49663.2026.11409347","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isscc49663.2026.11409347","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2026 IEEE International Solid-State Circuits Conference (ISSCC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.7609074115753174,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W2133563079","https://openalex.org/W2543533520","https://openalex.org/W2963255460","https://openalex.org/W2965444073","https://openalex.org/W4386090486","https://openalex.org/W4392739458","https://openalex.org/W4392746141","https://openalex.org/W4392746406","https://openalex.org/W4392746564","https://openalex.org/W4401881618","https://openalex.org/W4408182986","https://openalex.org/W4408183089","https://openalex.org/W4412962799"],"related_works":[],"abstract_inverted_index":{"A":[0],"manycore":[1],"DNN":[2,70],"processor":[3,71],"leverages":[4],"hybrid":[5],"bonding":[6],"in":[7],"a$14":[8],"\\times":[9,11,46],"4":[10],"2$mesh":[12],"network":[13],"on":[14,53],"chip":[15],"to":[16,25,34,59],"increase":[17],"3D":[18],"bandwidth":[19],"between":[20],"cores,":[21],"accelerators,":[22],"and":[23],"SRAM":[24],"2.5Tb/s/mm2.":[26],"Memory":[27],"throughput":[28],"is":[29],"improved":[30],"by":[31],"39%":[32],"compared":[33],"an":[35],"equivalent":[36],"2D":[37],"design":[38],"with":[39],"the":[40,78],"same":[41],"memory":[42],"capacity.":[43],"The":[44,69],"56$16":[45],"16$INT8":[47],"systolic":[48],"array":[49],"accelerators":[50],"are":[51],"stacked":[52],"top":[54],"of":[55,66],"56":[56],"RISC-V":[57],"cores":[58],"enable":[60],"a":[61,73],"peak":[62],"AI":[63],"performance":[64],"density":[65],"12.1":[67],"TOPS/mm2.":[68],"scores":[72],"latency":[74],"of$53":[75],"\\mu":[76],"\\mathrm{s}$on":[77],"image":[79],"classification":[80],"benchmark":[81],"from":[82],"MLPerf.":[83]},"counts_by_year":[],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2026-03-04T00:00:00"}