{"id":"https://openalex.org/W7133300855","doi":"https://doi.org/10.1109/isscc49663.2026.11409316","title":"A 2nm Clock-Edge Architecture for Processor Clock-Power Reduction","display_name":"A 2nm Clock-Edge Architecture for Processor Clock-Power Reduction","publication_year":2026,"publication_date":"2026-02-15","ids":{"openalex":"https://openalex.org/W7133300855","doi":"https://doi.org/10.1109/isscc49663.2026.11409316"},"language":null,"primary_location":{"id":"doi:10.1109/isscc49663.2026.11409316","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isscc49663.2026.11409316","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2026 IEEE International Solid-State Circuits Conference (ISSCC)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5025728433","display_name":"Yimai Peng","orcid":"https://orcid.org/0000-0001-9860-0175"},"institutions":[{"id":"https://openalex.org/I4210087596","display_name":"Qualcomm (United States)","ror":"https://ror.org/002zrf773","country_code":"US","type":"company","lineage":["https://openalex.org/I4210087596"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Yimai Peng","raw_affiliation_strings":["Qualcomm,Raleigh,NC"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Qualcomm,Raleigh,NC","institution_ids":["https://openalex.org/I4210087596"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5038164519","display_name":"Daniel Yingling","orcid":null},"institutions":[{"id":"https://openalex.org/I4210087596","display_name":"Qualcomm (United States)","ror":"https://ror.org/002zrf773","country_code":"US","type":"company","lineage":["https://openalex.org/I4210087596"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Daniel Yingling","raw_affiliation_strings":["Qualcomm,Raleigh,NC"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Qualcomm,Raleigh,NC","institution_ids":["https://openalex.org/I4210087596"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5006289520","display_name":"Basma Hajri","orcid":"https://orcid.org/0000-0002-7989-1365"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Basma Hajri","raw_affiliation_strings":["Qualcomm,Cork,Ireland"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Qualcomm,Cork,Ireland","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5094136757","display_name":"Robert J. Vachon","orcid":null},"institutions":[{"id":"https://openalex.org/I4210087596","display_name":"Qualcomm (United States)","ror":"https://ror.org/002zrf773","country_code":"US","type":"company","lineage":["https://openalex.org/I4210087596"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Robert Vachon","raw_affiliation_strings":["Qualcomm,Raleigh,NC"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Qualcomm,Raleigh,NC","institution_ids":["https://openalex.org/I4210087596"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5032038973","display_name":"Fikre Tsigabu Gebreyohannes","orcid":"https://orcid.org/0000-0001-7149-9556"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Fikre Gebreyohannes","raw_affiliation_strings":["Qualcomm,Cork,Ireland"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Qualcomm,Cork,Ireland","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5127982450","display_name":"Vincent Li","orcid":null},"institutions":[{"id":"https://openalex.org/I4210087596","display_name":"Qualcomm (United States)","ror":"https://ror.org/002zrf773","country_code":"US","type":"company","lineage":["https://openalex.org/I4210087596"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Vincent Li","raw_affiliation_strings":["Qualcomm,San Diego,CA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Qualcomm,San Diego,CA","institution_ids":["https://openalex.org/I4210087596"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5127949789","display_name":"Ghanshyam Chhetri","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Ghanshyam Chhetri","raw_affiliation_strings":["Qualcomm,Bangalore,India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Qualcomm,Bangalore,India","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5128000983","display_name":"Keith Bowman","orcid":null},"institutions":[{"id":"https://openalex.org/I4210087596","display_name":"Qualcomm (United States)","ror":"https://ror.org/002zrf773","country_code":"US","type":"company","lineage":["https://openalex.org/I4210087596"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Keith Bowman","raw_affiliation_strings":["Qualcomm,Raleigh,NC"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Qualcomm,Raleigh,NC","institution_ids":["https://openalex.org/I4210087596"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"172","last_page":"174"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.8932999968528748,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.8932999968528748,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.018799999728798866,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.01860000006854534,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.6043000221252441},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.5066999793052673},{"id":"https://openalex.org/keywords/controller","display_name":"Controller (irrigation)","score":0.4880000054836273},{"id":"https://openalex.org/keywords/clock-rate","display_name":"Clock rate","score":0.4235999882221222},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.36550000309944153},{"id":"https://openalex.org/keywords/digital-clock-manager","display_name":"Digital clock manager","score":0.3546999990940094},{"id":"https://openalex.org/keywords/clock-generator","display_name":"Clock generator","score":0.3246000111103058},{"id":"https://openalex.org/keywords/clock-gating","display_name":"Clock gating","score":0.31940001249313354}],"concepts":[{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.6043000221252441},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.5066999793052673},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4984000027179718},{"id":"https://openalex.org/C203479927","wikidata":"https://www.wikidata.org/wiki/Q5165939","display_name":"Controller (irrigation)","level":2,"score":0.4880000054836273},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4519999921321869},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.43560001254081726},{"id":"https://openalex.org/C178693496","wikidata":"https://www.wikidata.org/wiki/Q911691","display_name":"Clock rate","level":3,"score":0.4235999882221222},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.36550000309944153},{"id":"https://openalex.org/C113074038","wikidata":"https://www.wikidata.org/wiki/Q5276052","display_name":"Digital clock manager","level":5,"score":0.3546999990940094},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.34850001335144043},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.33660000562667847},{"id":"https://openalex.org/C2778023540","wikidata":"https://www.wikidata.org/wiki/Q2164847","display_name":"Clock generator","level":4,"score":0.3246000111103058},{"id":"https://openalex.org/C22716491","wikidata":"https://www.wikidata.org/wiki/Q590170","display_name":"Clock gating","level":5,"score":0.31940001249313354},{"id":"https://openalex.org/C79403827","wikidata":"https://www.wikidata.org/wiki/Q3988","display_name":"Real-time computing","level":1,"score":0.3165999948978424},{"id":"https://openalex.org/C173018170","wikidata":"https://www.wikidata.org/wiki/Q165678","display_name":"Microcontroller","level":2,"score":0.3093000054359436},{"id":"https://openalex.org/C81988521","wikidata":"https://www.wikidata.org/wiki/Q676838","display_name":"Control unit","level":2,"score":0.3003999888896942},{"id":"https://openalex.org/C192082776","wikidata":"https://www.wikidata.org/wiki/Q7663751","display_name":"System time","level":3,"score":0.2879999876022339},{"id":"https://openalex.org/C117551214","wikidata":"https://www.wikidata.org/wiki/Q6692774","display_name":"Low-power electronics","level":4,"score":0.2872999906539917},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.275299996137619},{"id":"https://openalex.org/C107464732","wikidata":"https://www.wikidata.org/wiki/Q235781","display_name":"Adaptive control","level":3,"score":0.2689000070095062},{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.2653999924659729},{"id":"https://openalex.org/C125576049","wikidata":"https://www.wikidata.org/wiki/Q2246273","display_name":"CPU multiplier","level":5,"score":0.26420000195503235},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.26269999146461487},{"id":"https://openalex.org/C65595194","wikidata":"https://www.wikidata.org/wiki/Q1000863","display_name":"Master clock","level":4,"score":0.2556999921798706},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.2524999976158142}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isscc49663.2026.11409316","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isscc49663.2026.11409316","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2026 IEEE International Solid-State Circuits Conference (ISSCC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.8745059370994568}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":20,"referenced_works":["https://openalex.org/W2039473024","https://openalex.org/W2113092930","https://openalex.org/W2117880765","https://openalex.org/W2139250338","https://openalex.org/W2142766971","https://openalex.org/W2148105517","https://openalex.org/W2149735769","https://openalex.org/W2159533695","https://openalex.org/W2166009017","https://openalex.org/W2171016590","https://openalex.org/W2512011691","https://openalex.org/W2619517799","https://openalex.org/W3008279770","https://openalex.org/W4236892114","https://openalex.org/W4237249613","https://openalex.org/W4323797080","https://openalex.org/W4392746363","https://openalex.org/W4401879750","https://openalex.org/W4409473913","https://openalex.org/W4412567145"],"related_works":[],"abstract_inverted_index":{"A":[0],"2nm":[1],"clock-edge":[2],"architecture":[3],"(CEA)":[4],"for":[5],"an":[6,19],"NPU":[7],"matrix-multiplication":[8],"unit":[9],"(MXU)":[10],"features":[11],"dual-edge-triggered":[12],"(DET)":[13],"flip-flops,":[14],"DET":[15],"clock-gating":[16],"circuits,":[17],"and":[18,54],"adaptive":[20],"clock":[21,37,52],"duty-cycle":[22],"controller":[23],"to":[24,72],"achieve":[25],"iso-performance":[26],"as":[27,70],"a":[28,55],"conventional":[29],"(CNV)":[30],"design":[31],"while":[32],"operating":[33],"at":[34,76],"half":[35],"the":[36,42,68,73],"frequency.":[38],"Silicon":[39],"measurements":[40],"of":[41,60],"CEA":[43],"MXU":[44,75],"demonstrate":[45],"<tex":[46,61],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[47,62],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">$\\sim":[48,63],"39-40":[49],"\\%$</tex>":[50],"lower":[51],"power":[53,58],"total":[56],"dynamic":[57],"reduction":[59],"7-15":[64],"\\%$</tex>,":[65],"depending":[66],"on":[67],"workload,":[69],"compared":[71],"CNV":[74],"iso-throughput.":[77]},"counts_by_year":[],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2026-03-04T00:00:00"}