{"id":"https://openalex.org/W7133305309","doi":"https://doi.org/10.1109/isscc49663.2026.11409125","title":"A 14GHz Ring-Based 3 <sup>rd</sup> -Order Fractional-N PLL with 164fs <sub>rms</sub> Jitter and a 100MHz Reference","display_name":"A 14GHz Ring-Based 3 <sup>rd</sup> -Order Fractional-N PLL with 164fs <sub>rms</sub> Jitter and a 100MHz Reference","publication_year":2026,"publication_date":"2026-02-15","ids":{"openalex":"https://openalex.org/W7133305309","doi":"https://doi.org/10.1109/isscc49663.2026.11409125"},"language":null,"primary_location":{"id":"doi:10.1109/isscc49663.2026.11409125","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isscc49663.2026.11409125","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2026 IEEE International Solid-State Circuits Conference (ISSCC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101931482","display_name":"Z. Z. Zhu","orcid":"https://orcid.org/0009-0000-0810-1648"},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"Zhaochen Zhu","raw_affiliation_strings":["Hong Kong University of Science and Technology,Guangzhou,China"],"affiliations":[{"raw_affiliation_string":"Hong Kong University of Science and Technology,Guangzhou,China","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101779147","display_name":"Qing Lin","orcid":"https://orcid.org/0000-0001-5150-6552"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Qingxuan Lin","raw_affiliation_strings":["Hong Kong University of Science and Technology,Guangzhou,China"],"affiliations":[{"raw_affiliation_string":"Hong Kong University of Science and Technology,Guangzhou,China","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5127873144","display_name":"Zhiqiang Huang","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Zhiqiang Huang","raw_affiliation_strings":["Hong Kong University of Science and Technology,Guangzhou,China"],"affiliations":[{"raw_affiliation_string":"Hong Kong University of Science and Technology,Guangzhou,China","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5101931482"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.89237641,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"470","last_page":"472"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9704999923706055,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9704999923706055,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.0031999999191612005,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.002099999925121665,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.8726000189781189},{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.6917999982833862},{"id":"https://openalex.org/keywords/bandwidth","display_name":"Bandwidth (computing)","score":0.5442000031471252},{"id":"https://openalex.org/keywords/integrator","display_name":"Integrator","score":0.5439000129699707},{"id":"https://openalex.org/keywords/calibration","display_name":"Calibration","score":0.4277999997138977},{"id":"https://openalex.org/keywords/control-theory","display_name":"Control theory (sociology)","score":0.36039999127388}],"concepts":[{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.8726000189781189},{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.6917999982833862},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.6424000263214111},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.5442000031471252},{"id":"https://openalex.org/C79518650","wikidata":"https://www.wikidata.org/wiki/Q2081431","display_name":"Integrator","level":3,"score":0.5439000129699707},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.510200023651123},{"id":"https://openalex.org/C165838908","wikidata":"https://www.wikidata.org/wiki/Q736777","display_name":"Calibration","level":2,"score":0.4277999997138977},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.36340001225471497},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.36090001463890076},{"id":"https://openalex.org/C47446073","wikidata":"https://www.wikidata.org/wiki/Q5165890","display_name":"Control theory (sociology)","level":3,"score":0.36039999127388},{"id":"https://openalex.org/C77881186","wikidata":"https://www.wikidata.org/wiki/Q7119642","display_name":"PLL multibit","level":4,"score":0.35339999198913574},{"id":"https://openalex.org/C89631360","wikidata":"https://www.wikidata.org/wiki/Q1428766","display_name":"Phase noise","level":2,"score":0.3402000069618225},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.32409998774528503},{"id":"https://openalex.org/C77170095","wikidata":"https://www.wikidata.org/wiki/Q1753188","display_name":"Linearity","level":2,"score":0.29739999771118164},{"id":"https://openalex.org/C190462668","wikidata":"https://www.wikidata.org/wiki/Q492265","display_name":"Delay-locked loop","level":4,"score":0.288100004196167},{"id":"https://openalex.org/C204323151","wikidata":"https://www.wikidata.org/wiki/Q905424","display_name":"Range (aeronautics)","level":2,"score":0.2614000141620636}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isscc49663.2026.11409125","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isscc49663.2026.11409125","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2026 IEEE International Solid-State Circuits Conference (ISSCC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W2768588921","https://openalex.org/W2780454010","https://openalex.org/W2966202279","https://openalex.org/W3134627429","https://openalex.org/W3201131231","https://openalex.org/W4210468261","https://openalex.org/W4220841253","https://openalex.org/W4360606005","https://openalex.org/W4408183347"],"related_works":[],"abstract_inverted_index":{"This":[0],"work":[1],"presents":[2],"a":[3,21],"14":[4],"GHz":[5],"ring-based":[6],"<tex":[7,14],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[8,15],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">$3^{\\text{rd":[9],"}}$</tex>-order":[10],"fractional-N":[11],"PLL":[12,33],"with":[13],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">$164":[16],"\\text{fs}_{\\text{rms":[17],"}}$</tex>":[18],"jitter":[19],"and":[20,38,65,78],"100":[22],"MHz":[23],"reference.":[24],"A":[25,41,54],"sub-sampling":[26,48],"DLL":[27,49],"is":[28,44,58,70],"cascaded":[29],"in":[30,46],"the":[31,47,62,74,80],"type-II":[32],"output":[34],"for":[35],"extra":[36],"phase-noise":[37],"supply-noise":[39],"suppression.":[40],"narrow-pulsed":[42],"integrator":[43],"used":[45],"to":[50,60,72],"reduce":[51,61,73],"integrated":[52],"jitter.":[53],"tri-state":[55],"polarity-reversible":[56],"SSPD":[57],"employed":[59],"DTC":[63],"range":[64,77],"bandwidth":[66],"degradation.":[67],"Delay":[68],"calibration":[69],"applied":[71],"VCDL":[75,81],"delay":[76],"implement":[79],"duty-cycle":[82],"calibration.":[83]},"counts_by_year":[],"updated_date":"2026-03-05T07:30:30.508283","created_date":"2026-03-04T00:00:00"}
