{"id":"https://openalex.org/W7133323434","doi":"https://doi.org/10.1109/isscc49663.2026.11409120","title":"A 48Gb/s/lane 1.24Tb/s/mm UCIe-Compliant Die-to-Die Link Over 30mm Standard Package","display_name":"A 48Gb/s/lane 1.24Tb/s/mm UCIe-Compliant Die-to-Die Link Over 30mm Standard Package","publication_year":2026,"publication_date":"2026-02-15","ids":{"openalex":"https://openalex.org/W7133323434","doi":"https://doi.org/10.1109/isscc49663.2026.11409120"},"language":null,"primary_location":{"id":"doi:10.1109/isscc49663.2026.11409120","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isscc49663.2026.11409120","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2026 IEEE International Solid-State Circuits Conference (ISSCC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5051922982","display_name":"Susnata Mondal","orcid":"https://orcid.org/0000-0002-8865-7132"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Susnata Mondal","raw_affiliation_strings":["Intel,Hillsboro,OR"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel,Hillsboro,OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5014099014","display_name":"Sashank Krishnamurthy","orcid":"https://orcid.org/0000-0003-3091-0016"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sashank Krishnamurthy","raw_affiliation_strings":["Intel,Hillsboro,OR"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel,Hillsboro,OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5127953500","display_name":"Shuhei Yamada","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Shuhei Yamada","raw_affiliation_strings":["Intel,Hillsboro,OR"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel,Hillsboro,OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5039671584","display_name":"Zhaokai Liu","orcid":"https://orcid.org/0000-0002-7046-7998"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Zhaokai Liu","raw_affiliation_strings":["Intel,Santa Clara,CA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel,Santa Clara,CA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5128005403","display_name":"Junyi Qiu","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Junyi Qiu","raw_affiliation_strings":["Intel,Hillsboro,OR"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel,Hillsboro,OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5127908017","display_name":"Soumya Bose","orcid":null},"institutions":[{"id":"https://openalex.org/I185103710","display_name":"University of California, Santa Cruz","ror":"https://ror.org/03s65by71","country_code":"US","type":"education","lineage":["https://openalex.org/I185103710"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Soumya Bose","raw_affiliation_strings":["University of California,Santa Cruz,CA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of California,Santa Cruz,CA","institution_ids":["https://openalex.org/I185103710"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5037121757","display_name":"Zuoguo Wu","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Zuoguo Wu","raw_affiliation_strings":["Intel,Santa Clara,CA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel,Santa Clara,CA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5037531724","display_name":"Gerald Pasdast","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Gerald Pasdast","raw_affiliation_strings":["Intel,Santa Clara,CA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel,Santa Clara,CA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5090419770","display_name":"James Jaussi","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"James Jaussi","raw_affiliation_strings":["Intel,Hillsboro,OR"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel,Hillsboro,OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5053540874","display_name":"Mozhgan Mansuri","orcid":"https://orcid.org/0000-0002-0277-7775"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Mozhgan Mansuri","raw_affiliation_strings":["Intel,Hillsboro,OR"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel,Hillsboro,OR","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":10,"corresponding_author_ids":["https://openalex.org/A5051922982"],"corresponding_institution_ids":["https://openalex.org/I1343180700"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.39980146,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"134","last_page":"136"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.45559999346733093,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.45559999346733093,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.19329999387264252,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11429","display_name":"Semiconductor Lasers and Optical Devices","score":0.14020000398159027,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/integrated-circuit-packaging","display_name":"Integrated circuit packaging","score":0.436599999666214},{"id":"https://openalex.org/keywords/work","display_name":"Work (physics)","score":0.4309999942779541},{"id":"https://openalex.org/keywords/phy","display_name":"PHY","score":0.4244000017642975},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.4104999899864197},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.31769999861717224},{"id":"https://openalex.org/keywords/printed-circuit-board","display_name":"Printed circuit board","score":0.29670000076293945}],"concepts":[{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5130000114440918},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.47510001063346863},{"id":"https://openalex.org/C186260285","wikidata":"https://www.wikidata.org/wiki/Q759494","display_name":"Integrated circuit packaging","level":3,"score":0.436599999666214},{"id":"https://openalex.org/C18762648","wikidata":"https://www.wikidata.org/wiki/Q42213","display_name":"Work (physics)","level":2,"score":0.4309999942779541},{"id":"https://openalex.org/C41918916","wikidata":"https://www.wikidata.org/wiki/Q192727","display_name":"PHY","level":4,"score":0.4244000017642975},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.4104999899864197},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.38370001316070557},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.337799996137619},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.32190001010894775},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.31769999861717224},{"id":"https://openalex.org/C120793396","wikidata":"https://www.wikidata.org/wiki/Q173350","display_name":"Printed circuit board","level":2,"score":0.29670000076293945},{"id":"https://openalex.org/C2778753846","wikidata":"https://www.wikidata.org/wiki/Q6554239","display_name":"Link (geometry)","level":2,"score":0.2847999930381775},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.26249998807907104},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.25279998779296875}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isscc49663.2026.11409120","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isscc49663.2026.11409120","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2026 IEEE International Solid-State Circuits Conference (ISSCC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.5775967240333557,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W2227038539","https://openalex.org/W2513352037","https://openalex.org/W2790928636","https://openalex.org/W2899956174","https://openalex.org/W3133724345","https://openalex.org/W4210269761","https://openalex.org/W4220804507","https://openalex.org/W4392739445","https://openalex.org/W4401880686","https://openalex.org/W4409991368","https://openalex.org/W4412965099"],"related_works":[],"abstract_inverted_index":{"This":[0],"work":[1],"demonstrates":[2],"a":[3,32],"UCle-S":[4],"compliant":[5],"die-to-die":[6],"PHY":[7],"at":[8,37],"<tex":[9,20,38,46,84,92],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[10,21,39,47,85,93],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">$48\\text{Gb}":[11],"/":[12,24,26,42,50,53],"\\mathrm{s}":[13,25],"/$</tex>":[14],"lane":[15],"across":[16],"16":[17],"lanes,":[18],"achieving":[19],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">$1.24":[22],"\\text{Tb}":[23],"\\text{mm}$</tex>":[27],"shoreline":[28],"BW":[29,97],"density":[30],"over":[31],"30":[33],"mm":[34],"organic":[35],"package":[36],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">$1.2":[40],"\\text{pJ}":[41,52],"\\mathrm{b}$</tex>,":[43],"extendable":[44],"to":[45,79],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">$56":[48],"\\text{GT}":[49],"\\mathrm{s}(1.13":[51],"\\mathrm{b})$</tex>.":[54],"Circuit":[55],"innovations":[56],"include":[57],"an":[58],"impedance-invariant":[59],"TX":[60],"CTLE,":[61],"high-swing":[62],"N/N":[63],"driver,":[64],"compact":[65],"resonant":[66],"clocking,":[67],"double-tail":[68],"latch":[69],"w/":[70],"improved":[71],"setup/hold":[72],"times,":[73],"and":[74,91],"common-mode":[75],"supply-noise":[76],"rejection.":[77],"Compared":[78],"prior":[80],"UCle-S,":[81],"it":[82],"achieves":[83],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">$3":[86],"\\times$</tex>":[87,95],"higher":[88,96],"data":[89],"rate":[90],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">$2.8":[94],"density.":[98]},"counts_by_year":[],"updated_date":"2026-05-05T08:41:31.759640","created_date":"2026-03-04T00:00:00"}