{"id":"https://openalex.org/W4221033610","doi":"https://doi.org/10.1109/isscc42614.2022.9731747","title":"A 56GHz 23mW Fractional-N PLL with 110fs Jitter","display_name":"A 56GHz 23mW Fractional-N PLL with 110fs Jitter","publication_year":2022,"publication_date":"2022-02-20","ids":{"openalex":"https://openalex.org/W4221033610","doi":"https://doi.org/10.1109/isscc42614.2022.9731747"},"language":"en","primary_location":{"is_oa":false,"landing_page_url":"https://doi.org/10.1109/isscc42614.2022.9731747","pdf_url":null,"source":{"id":"https://openalex.org/S4363607897","display_name":"2022 IEEE International Solid- State Circuits Conference (ISSCC)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"version":null,"is_accepted":false,"is_published":false},"type":"article","type_crossref":"proceedings-article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5055056689","display_name":"Yu Zhao","orcid":"https://orcid.org/0000-0003-4377-5298"},"institutions":[{"id":"https://openalex.org/I161318765","display_name":"University of California, Los Angeles","ror":"https://ror.org/046rm7j60","country_code":"US","type":"education","lineage":["https://openalex.org/I161318765","https://openalex.org/I2803209242"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Yu Zhao","raw_affiliation_string":"University of California, Los Angeles, CA","raw_affiliation_strings":["University of California, Los Angeles, CA"]},{"author_position":"middle","author":{"id":"https://openalex.org/A5082183044","display_name":"Onur Memioglu","orcid":"https://orcid.org/0000-0002-5185-444X"},"institutions":[{"id":"https://openalex.org/I161318765","display_name":"University of California, Los Angeles","ror":"https://ror.org/046rm7j60","country_code":"US","type":"education","lineage":["https://openalex.org/I161318765","https://openalex.org/I2803209242"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Onur Memioglu","raw_affiliation_string":"University of California, Los Angeles, CA","raw_affiliation_strings":["University of California, Los Angeles, CA"]},{"author_position":"last","author":{"id":"https://openalex.org/A5042508406","display_name":"Behzad Razavi","orcid":"https://orcid.org/0000-0003-1168-9205"},"institutions":[{"id":"https://openalex.org/I161318765","display_name":"University of California, Los Angeles","ror":"https://ror.org/046rm7j60","country_code":"US","type":"education","lineage":["https://openalex.org/I161318765","https://openalex.org/I2803209242"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Behzad Razavi","raw_affiliation_string":"University of California, Los Angeles, CA","raw_affiliation_strings":["University of California, Los Angeles, CA"]}],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"has_fulltext":false,"cited_by_count":1,"cited_by_percentile_year":{"min":68,"max":78},"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Phase-Locked Loops in High-Speed Circuits","score":0.9994,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Phase-Locked Loops in High-Speed Circuits","score":0.9994,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Atomic Layer Deposition Technology","score":0.9881,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9878,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"keyword":"jitter","score":0.4236}],"concepts":[{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.9438936},{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.90578574},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.502814},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4914328},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.42757922},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.41565123},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.41527116},{"id":"https://openalex.org/C77881186","wikidata":"https://www.wikidata.org/wiki/Q7119642","display_name":"PLL multibit","level":4,"score":0.41244674},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.3378055},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.29725677},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.21343786},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.15737054},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"is_oa":false,"landing_page_url":"https://doi.org/10.1109/isscc42614.2022.9731747","pdf_url":null,"source":{"id":"https://openalex.org/S4363607897","display_name":"2022 IEEE International Solid- State Circuits Conference (ISSCC)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"version":null,"is_accepted":false,"is_published":false}],"best_oa_location":null,"sustainable_development_goals":[],"grants":[],"referenced_works_count":1,"referenced_works":["https://openalex.org/W3183913092"],"related_works":["https://openalex.org/W188830667","https://openalex.org/W1605914315","https://openalex.org/W4360861688","https://openalex.org/W1977306627","https://openalex.org/W3134930219","https://openalex.org/W984417604","https://openalex.org/W2498262093","https://openalex.org/W2139484866","https://openalex.org/W2188779191","https://openalex.org/W2967785526"],"ngrams_url":"https://api.openalex.org/works/W4221033610/ngrams","abstract_inverted_index":{"PAM-4":[0],"wireline":[1],"transmitters":[2],"operating":[3],"at":[4],"224Gb/s":[5],"can":[6,88],"employ":[7],"a":[8,32,64,73,83,127,130],"56GHz":[9,74],"PLL":[10,24,49,86,128],"for":[11,82],"multiplexing.":[12],"Such":[13],"an":[14,139],"environment":[15],"poses":[16],"several":[17],"constraints":[18],"on":[19],"the":[20,23,36,48,80],"design.":[21],"First,":[22],"rms":[25,103],"jitter":[26,131],"must":[27],"be":[28,89],"no":[29],"more":[30],"than":[31],"few":[33],"percent":[34],"of":[35,132,141],"symbol":[37],"period,":[38],"8.93ps,":[39],"dictating":[40],"values":[41],"around":[42],"$100\\text{fs}_{\\text{rms}}$":[45],".":[46],"Second,":[47],"should":[50],"preferably":[51],"provide":[52],"fractional-N":[53,95],"operation":[54],"so":[55],"as":[56],"to":[57,70,108,121],"accommodate":[58],"different":[59],"crystal":[60],"frequencies.":[61],"Third,":[62],"in":[63,97,147],"multi-lane":[65],"system,":[66],"it":[67],"is":[68],"desirable":[69],"avoid":[71],"distributing":[72],"clock":[75],"over":[76],"long":[77],"interconnects,":[78],"hence":[79],"need":[81],"lower-power,":[84],"compact":[85],"that":[87,134],"used":[90],"within":[91],"each":[92],"lane.":[93],"Prior":[94],"designs":[96],"this":[98],"frequency":[99],"range":[100],"have":[101],"achieved":[102],"jitters":[104],"ranging":[105],"from":[106,119],"200":[107],"500fs":[109],"while":[110],"consuming":[111],"beween":[112],"31":[113],"and":[114,116,137],"46mW":[115],"occupying":[117],"areas":[118],"0.38":[120],"0.55mm2":[122],"[1]\u2013[4].":[123],"This":[124],"paper":[125],"introduces":[126],"with":[129],"110fs":[133],"draws":[135],"23mW":[136],"occupies":[138],"area":[140],"0.1":[142],"mm":[143],"2":[146],"28nm":[148],"CMOS":[149],"technology.":[150]},"cited_by_api_url":"https://api.openalex.org/works?filter=cites:W4221033610","counts_by_year":[{"year":2023,"cited_by_count":1}],"updated_date":"2024-03-21T23:51:29.431965","created_date":"2022-04-03"}