{"id":"https://openalex.org/W4220717521","doi":"https://doi.org/10.1109/isscc42614.2022.9731560","title":"A 2-to-2.48GHz Voltage-Interpolator-Based Fractional-N Type-I Sampling PLL in 22nm FinFET Assisting Fast Crystal Startup","display_name":"A 2-to-2.48GHz Voltage-Interpolator-Based Fractional-N Type-I Sampling PLL in 22nm FinFET Assisting Fast Crystal Startup","publication_year":2022,"publication_date":"2022-02-20","ids":{"openalex":"https://openalex.org/W4220717521","doi":"https://doi.org/10.1109/isscc42614.2022.9731560"},"language":"en","primary_location":{"id":"doi:10.1109/isscc42614.2022.9731560","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isscc42614.2022.9731560","pdf_url":null,"source":{"id":"https://openalex.org/S4363607897","display_name":"2022 IEEE International Solid- State Circuits Conference (ISSCC)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2022 IEEE International Solid- State Circuits Conference (ISSCC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5078845675","display_name":"Somnath Kundu","orcid":"https://orcid.org/0000-0002-5891-7968"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Somnath Kundu","raw_affiliation_strings":["Intel,Hillsboro,OR","Intel, Hillsboro, OR"],"affiliations":[{"raw_affiliation_string":"Intel,Hillsboro,OR","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5002153488","display_name":"Timo Huusari","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Timo Huusari","raw_affiliation_strings":["Intel,Hillsboro,OR","Intel, Hillsboro, OR"],"affiliations":[{"raw_affiliation_string":"Intel,Hillsboro,OR","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5075138756","display_name":"Hao Luo","orcid":"https://orcid.org/0000-0001-9515-1458"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Hao Luo","raw_affiliation_strings":["Intel,Hillsboro,OR","Intel, Hillsboro, OR"],"affiliations":[{"raw_affiliation_string":"Intel,Hillsboro,OR","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101549972","display_name":"Abhishek Agrawal","orcid":"https://orcid.org/0000-0003-4831-7982"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Abhishek Agrawal","raw_affiliation_strings":["Intel,Hillsboro,OR","Intel, Hillsboro, OR"],"affiliations":[{"raw_affiliation_string":"Intel,Hillsboro,OR","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5002214786","display_name":"Eduardo Alban","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Eduardo Alban","raw_affiliation_strings":["Intel,Hillsboro,OR","Intel, Hillsboro, OR"],"affiliations":[{"raw_affiliation_string":"Intel,Hillsboro,OR","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5005041408","display_name":"Sarah Shahraini","orcid":"https://orcid.org/0000-0001-8609-2505"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sarah Shahraini","raw_affiliation_strings":["Intel,Hillsboro,OR","Intel, Hillsboro, OR"],"affiliations":[{"raw_affiliation_string":"Intel,Hillsboro,OR","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5073964639","display_name":"Thao Xiong","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Thao Xiong","raw_affiliation_strings":["Intel,Hillsboro,OR","Intel, Hillsboro, OR"],"affiliations":[{"raw_affiliation_string":"Intel,Hillsboro,OR","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5028630331","display_name":"Dan Lake","orcid":"https://orcid.org/0000-0002-2590-1900"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Dan Lake","raw_affiliation_strings":["Intel,Hillsboro,OR","Intel, Hillsboro, OR"],"affiliations":[{"raw_affiliation_string":"Intel,Hillsboro,OR","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5065695022","display_name":"Stefano Pellerano","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Stefano Pellerano","raw_affiliation_strings":["Intel,Hillsboro,OR","Intel, Hillsboro, OR"],"affiliations":[{"raw_affiliation_string":"Intel,Hillsboro,OR","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5083136218","display_name":"Jason Mix","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jason Mix","raw_affiliation_strings":["Intel,Hillsboro,OR","Intel, Hillsboro, OR"],"affiliations":[{"raw_affiliation_string":"Intel,Hillsboro,OR","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5034919212","display_name":"Nasser Kurd","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Nasser Kurd","raw_affiliation_strings":["Intel,Hillsboro,OR","Intel, Hillsboro, OR"],"affiliations":[{"raw_affiliation_string":"Intel,Hillsboro,OR","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5110280562","display_name":"M.A. Abdelmoneum","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Mohamed Abdel-moneum","raw_affiliation_strings":["Intel,Hillsboro,OR","Intel, Hillsboro, OR"],"affiliations":[{"raw_affiliation_string":"Intel,Hillsboro,OR","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5059381050","display_name":"Brent Carlton","orcid":"https://orcid.org/0000-0003-4542-4715"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Brent Carlton","raw_affiliation_strings":["Intel,Hillsboro,OR","Intel, Hillsboro, OR"],"affiliations":[{"raw_affiliation_string":"Intel,Hillsboro,OR","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":13,"corresponding_author_ids":["https://openalex.org/A5078845675"],"corresponding_institution_ids":["https://openalex.org/I1343180700"],"apc_list":null,"apc_paid":null,"fwci":3.2224,"has_fulltext":false,"cited_by_count":10,"citation_normalized_percentile":{"value":0.93499263,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"144","last_page":"146"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9930999875068665,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11429","display_name":"Semiconductor Lasers and Optical Devices","score":0.9914000034332275,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.7878486514091492},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.6366152167320251},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.5872296690940857},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5408528447151184},{"id":"https://openalex.org/keywords/integrator","display_name":"Integrator","score":0.47768455743789673},{"id":"https://openalex.org/keywords/sampling","display_name":"Sampling (signal processing)","score":0.4296034574508667},{"id":"https://openalex.org/keywords/capacitor","display_name":"Capacitor","score":0.42642027139663696},{"id":"https://openalex.org/keywords/oversampling","display_name":"Oversampling","score":0.42254117131233215},{"id":"https://openalex.org/keywords/phase-noise","display_name":"Phase noise","score":0.41117921471595764},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.382579505443573},{"id":"https://openalex.org/keywords/filter","display_name":"Filter (signal processing)","score":0.3125496804714203},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.312536358833313},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.30925875902175903},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.19224032759666443}],"concepts":[{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.7878486514091492},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.6366152167320251},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.5872296690940857},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5408528447151184},{"id":"https://openalex.org/C79518650","wikidata":"https://www.wikidata.org/wiki/Q2081431","display_name":"Integrator","level":3,"score":0.47768455743789673},{"id":"https://openalex.org/C140779682","wikidata":"https://www.wikidata.org/wiki/Q210868","display_name":"Sampling (signal processing)","level":3,"score":0.4296034574508667},{"id":"https://openalex.org/C52192207","wikidata":"https://www.wikidata.org/wiki/Q5322","display_name":"Capacitor","level":3,"score":0.42642027139663696},{"id":"https://openalex.org/C197323446","wikidata":"https://www.wikidata.org/wiki/Q331222","display_name":"Oversampling","level":3,"score":0.42254117131233215},{"id":"https://openalex.org/C89631360","wikidata":"https://www.wikidata.org/wiki/Q1428766","display_name":"Phase noise","level":2,"score":0.41117921471595764},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.382579505443573},{"id":"https://openalex.org/C106131492","wikidata":"https://www.wikidata.org/wiki/Q3072260","display_name":"Filter (signal processing)","level":2,"score":0.3125496804714203},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.312536358833313},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.30925875902175903},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.19224032759666443}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isscc42614.2022.9731560","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isscc42614.2022.9731560","pdf_url":null,"source":{"id":"https://openalex.org/S4363607897","display_name":"2022 IEEE International Solid- State Circuits Conference (ISSCC)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2022 IEEE International Solid- State Circuits Conference (ISSCC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8999999761581421,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":3,"referenced_works":["https://openalex.org/W3015520279","https://openalex.org/W3018467755","https://openalex.org/W3163190540"],"related_works":["https://openalex.org/W2899084033","https://openalex.org/W3176167732","https://openalex.org/W2167594209","https://openalex.org/W2920848205","https://openalex.org/W1972698597","https://openalex.org/W2591698638","https://openalex.org/W3135664810","https://openalex.org/W3015520279","https://openalex.org/W3205198652","https://openalex.org/W4220717521"],"abstract_inverted_index":{"A":[0,77,147],"high-performance":[1],"clock":[2],"generator":[3],"with":[4,128],"extremely":[5],"low":[6],"jitter,":[7],"area,":[8],"and":[9,55,116,136,204,224,240,303,335],"power":[10,250,256],"consumption":[11],"is":[12,216,229,265,354],"the":[13,18,40,104,108,122,134,182,193,205,225,243,263,271,317,325,343,350,359,365],"key":[14],"building":[15],"block":[16],"in":[17,45,74,153,170,186,280],"emerging":[19],"Internet":[20],"of":[21,27,107,242],"Things":[22],"(IoT)":[23],"to":[24,38,70,102,191,267,300,328,356,364],"connect":[25],"billions":[26],"devices.":[28],"Recently,":[29],"digital":[30],"phase-locked":[31],"loops":[32],"(DPLL)":[33],"[1,2]":[34],"have":[35],"been":[36],"developed":[37],"eliminate":[39,198],"bulky":[41],"loop":[42,137],"filter":[43],"(LF)":[44],"type-II":[46],"charge-pump":[47],"PLLs.":[48],"However,":[49],"they":[50],"suffer":[51],"from":[52],"quantization":[53],"noise":[54,87,215,334],"spurs,":[56],"requiring":[57,308],"complex":[58,207],"calibration":[59,167,208,312,346],"techniques.":[60],"Therefore,":[61],"type-I":[62,188],"reference-sampling":[63],"PLLs":[64],"are":[65,119,141,246],"gaining":[66],"popularity":[67],"[3,":[68],"4]":[69],"achieve":[71,192],"wider":[72],"bandwidths":[73],"smaller":[75],"areas.":[76],"passive":[78,220],"sampling":[79,189],"phase":[80,212],"detector":[81],"(SPD)":[82],"has":[83],"a":[84,90,94,98,166,176,187,199,219,232,261,288,321],"much":[85],"lower":[86],"contribution":[88],"than":[89],"charge":[91,184],"pump.":[92],"But,":[93],"fractional-N":[95,194],"implementation":[96],"requires":[97,165],"digital-to-time":[99],"converter":[100],"(DTC)":[101],"align":[103],"input":[105],"clocks":[106],"SPD":[109],"for":[110,144,235,248,273,283,338],"spur":[111],"mitigation":[112],"[3].":[113],"Precise":[114],"gain":[115],"nonlinearity":[117],"calibrations":[118],"needed":[120],"as":[121],"DTC":[123,200],"delay":[124],"can":[125],"vary":[126],"significantly":[127],"process-voltage-temperature":[129],"(PVT)":[130],"variations.":[131],"This":[132,173],"increases":[133],"complexity":[135],"convergence":[138],"time,":[139],"which":[140,163,294,353],"not":[142],"preferable":[143],"IoT":[145],"applications.":[146],"capacitive":[148],"digital-to-analog-converter":[149],"(CDAC)-based":[150],"approach":[151],"proposed":[152],"[4]":[154],"relies":[155],"on":[156,181],"an":[157,309],"accurate":[158],"voltage":[159,202],"reference":[160,203],"provided":[161],"externally,":[162],"also":[164],"across":[168,306],"PVT":[169],"practical":[171],"implementations.":[172],"work":[174],"presents":[175],"voltage-interpolation":[177],"(VI)":[178],"technique":[179],"based":[180],"capacitor":[183],"sharing":[185],"PLL":[190,264,322,371],"operation":[195],"and,":[196],"therefore,":[197],"or":[201],"associated":[206],"logic,":[209],"providing":[210,369],"fast":[211,238,284],"locking.":[213,372],"Furthermore,":[214],"minimized":[217],"using":[218],"switch-capacitor-based":[221],"VI":[222],"(SC-VI),":[223],"fractional":[226],"frequency-synthesis":[227],"resolution":[228],"enhanced":[230],"utilizing":[231],"AZ-VI.":[233],"Moreover,":[234],"edge-compute":[236],"platforms,":[237],"shutdown":[239],"restart":[241],"clocking":[244],"subsystem":[245],"necessary":[247],"efficient":[249],"management":[251],"by":[252],"transitioning":[253],"among":[254],"different":[255],"states.":[257],"To":[258],"enable":[259],"such":[260],"requirement,":[262],"reconfigured":[266],"inject":[268],"energy":[269,277],"into":[270],"crystal":[272,281,326],"quick":[274],"startup.":[275],"Prior":[276],"injection":[278],"techniques":[279],"oscillators":[282],"startup":[285,296,340],"[5]":[286],"used":[287],"dedicated":[289],"ring":[290],"voltage-controlled":[291],"oscillator":[292,327],"(VCO),":[293],"exhibited":[295],"time":[297],"uncertainty":[298],"due":[299],"high":[301],"jitter":[302],"frequency":[304,311,330,336,345,361],"drift":[305,337],"PVT,":[307],"additional":[310],"step.":[313,347],"In":[314,348],"contrast,":[315],"reusing":[316],"LC":[318],"VCO":[319,344,360],"inside":[320],"that":[323],"follows":[324],"perform":[329],"synthesis":[331],"introduces":[332],"less":[333],"robust":[339],"while":[341],"eliminating":[342],"addition,":[349],"chirp":[351],"mechanism,":[352],"similar":[355],"[5],":[357],"sets":[358],"very":[362],"close":[363],"desired":[366],"steady-state":[367],"value,":[368],"faster":[370]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":5},{"year":2023,"cited_by_count":3},{"year":2022,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}