{"id":"https://openalex.org/W3135839634","doi":"https://doi.org/10.1109/isscc42613.2021.9365926","title":"29.1 A 40nm 64Kb 56.67TOPS/W Read-Disturb-Tolerant Compute-in-Memory/Digital RRAM Macro with Active-Feedback-Based Read and In-Situ Write Verification","display_name":"29.1 A 40nm 64Kb 56.67TOPS/W Read-Disturb-Tolerant Compute-in-Memory/Digital RRAM Macro with Active-Feedback-Based Read and In-Situ Write Verification","publication_year":2021,"publication_date":"2021-02-13","ids":{"openalex":"https://openalex.org/W3135839634","doi":"https://doi.org/10.1109/isscc42613.2021.9365926","mag":"3135839634"},"language":"en","primary_location":{"id":"doi:10.1109/isscc42613.2021.9365926","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isscc42613.2021.9365926","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2021 IEEE International Solid- State Circuits Conference (ISSCC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5059199220","display_name":"Jong\u2010Hyeok Yoon","orcid":"https://orcid.org/0000-0001-7373-7028"},"institutions":[{"id":"https://openalex.org/I130701444","display_name":"Georgia Institute of Technology","ror":"https://ror.org/01zkghx44","country_code":"US","type":"education","lineage":["https://openalex.org/I130701444"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Jong-Hyeok Yoon","raw_affiliation_strings":["Georgia Institute of Technology, Atlanta, GA"],"affiliations":[{"raw_affiliation_string":"Georgia Institute of Technology, Atlanta, GA","institution_ids":["https://openalex.org/I130701444"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5078008152","display_name":"Muya Chang","orcid":"https://orcid.org/0000-0002-3035-1106"},"institutions":[{"id":"https://openalex.org/I130701444","display_name":"Georgia Institute of Technology","ror":"https://ror.org/01zkghx44","country_code":"US","type":"education","lineage":["https://openalex.org/I130701444"]},{"id":"https://openalex.org/I4210120917","display_name":"Taiwan Semiconductor Manufacturing Company (Taiwan)","ror":"https://ror.org/02wx79d08","country_code":"TW","type":"company","lineage":["https://openalex.org/I4210120917"]}],"countries":["TW","US"],"is_corresponding":false,"raw_author_name":"Muya Chang","raw_affiliation_strings":["Georgia Institute of Technology, Atlanta, GA","TSMC Corporate Research, Hsinchu, Taiwan"],"affiliations":[{"raw_affiliation_string":"Georgia Institute of Technology, Atlanta, GA","institution_ids":["https://openalex.org/I130701444"]},{"raw_affiliation_string":"TSMC Corporate Research, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I4210120917"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5083012416","display_name":"Win-San Khwa","orcid":"https://orcid.org/0000-0002-6283-3564"},"institutions":[{"id":"https://openalex.org/I4210120917","display_name":"Taiwan Semiconductor Manufacturing Company (Taiwan)","ror":"https://ror.org/02wx79d08","country_code":"TW","type":"company","lineage":["https://openalex.org/I4210120917"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Win-San Khwa","raw_affiliation_strings":["TSMC Corporate Research, Hsinchu, Taiwan"],"affiliations":[{"raw_affiliation_string":"TSMC Corporate Research, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I4210120917"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5109491324","display_name":"Yu-Der Chih","orcid":null},"institutions":[{"id":"https://openalex.org/I4210120917","display_name":"Taiwan Semiconductor Manufacturing Company (Taiwan)","ror":"https://ror.org/02wx79d08","country_code":"TW","type":"company","lineage":["https://openalex.org/I4210120917"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Yu-Der Chih","raw_affiliation_strings":["TSMC Design Technology, Hsinchu, Taiwan"],"affiliations":[{"raw_affiliation_string":"TSMC Design Technology, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I4210120917"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5023225287","display_name":"Meng\u2010Fan Chang","orcid":"https://orcid.org/0000-0001-6905-6350"},"institutions":[{"id":"https://openalex.org/I130701444","display_name":"Georgia Institute of Technology","ror":"https://ror.org/01zkghx44","country_code":"US","type":"education","lineage":["https://openalex.org/I130701444"]},{"id":"https://openalex.org/I4210120917","display_name":"Taiwan Semiconductor Manufacturing Company (Taiwan)","ror":"https://ror.org/02wx79d08","country_code":"TW","type":"company","lineage":["https://openalex.org/I4210120917"]}],"countries":["TW","US"],"is_corresponding":false,"raw_author_name":"Meng-Fan Chang","raw_affiliation_strings":["Georgia Institute of Technology, Atlanta, GA","TSMC Corporate Research, Hsinchu, Taiwan"],"affiliations":[{"raw_affiliation_string":"Georgia Institute of Technology, Atlanta, GA","institution_ids":["https://openalex.org/I130701444"]},{"raw_affiliation_string":"TSMC Corporate Research, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I4210120917"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5091408102","display_name":"Arijit Raychowdhury","orcid":"https://orcid.org/0000-0001-8391-0576"},"institutions":[{"id":"https://openalex.org/I130701444","display_name":"Georgia Institute of Technology","ror":"https://ror.org/01zkghx44","country_code":"US","type":"education","lineage":["https://openalex.org/I130701444"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Arijit Raychowdhury","raw_affiliation_strings":["Georgia Institute of Technology, Atlanta, GA"],"affiliations":[{"raw_affiliation_string":"Georgia Institute of Technology, Atlanta, GA","institution_ids":["https://openalex.org/I130701444"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5059199220"],"corresponding_institution_ids":["https://openalex.org/I130701444"],"apc_list":null,"apc_paid":null,"fwci":6.9187,"has_fulltext":false,"cited_by_count":82,"citation_normalized_percentile":{"value":0.97649679,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":99,"max":100},"biblio":{"volume":null,"issue":null,"first_page":"404","last_page":"406"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9958000183105469,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/resistive-random-access-memory","display_name":"Resistive random-access memory","score":0.946074366569519},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.7660292983055115},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.620478093624115},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6027290225028992},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5515258312225342},{"id":"https://openalex.org/keywords/random-access-memory","display_name":"Random access memory","score":0.4388422667980194},{"id":"https://openalex.org/keywords/non-volatile-memory","display_name":"Non-volatile memory","score":0.43695566058158875},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.40878811478614807},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3914513885974884},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.36485135555267334},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.3646308481693268},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.23694965243339539},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.12823358178138733}],"concepts":[{"id":"https://openalex.org/C182019814","wikidata":"https://www.wikidata.org/wiki/Q1143830","display_name":"Resistive random-access memory","level":3,"score":0.946074366569519},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.7660292983055115},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.620478093624115},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6027290225028992},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5515258312225342},{"id":"https://openalex.org/C2994168587","wikidata":"https://www.wikidata.org/wiki/Q5295","display_name":"Random access memory","level":2,"score":0.4388422667980194},{"id":"https://openalex.org/C177950962","wikidata":"https://www.wikidata.org/wiki/Q10997658","display_name":"Non-volatile memory","level":2,"score":0.43695566058158875},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.40878811478614807},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3914513885974884},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.36485135555267334},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.3646308481693268},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.23694965243339539},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.12823358178138733}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isscc42613.2021.9365926","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isscc42613.2021.9365926","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2021 IEEE International Solid- State Circuits Conference (ISSCC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320306087","display_name":"Semiconductor Research Corporation","ror":"https://ror.org/047z4n946"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W2584335437","https://openalex.org/W2794288888","https://openalex.org/W2920866490","https://openalex.org/W2921329602","https://openalex.org/W3015980402","https://openalex.org/W3016048022","https://openalex.org/W3048589487","https://openalex.org/W3049223108","https://openalex.org/W6775551420"],"related_works":["https://openalex.org/W2076211355","https://openalex.org/W2007070351","https://openalex.org/W2033811947","https://openalex.org/W2790329865","https://openalex.org/W2183989414","https://openalex.org/W1551399929","https://openalex.org/W1909296377","https://openalex.org/W2410132916","https://openalex.org/W2533127403","https://openalex.org/W2942190539"],"abstract_inverted_index":{"As":[0],"memory-centric":[1],"workloads":[2],"(AI,":[3],"graph-analytics)":[4],"continue":[5],"to":[6,26,62,81,87,92,148],"gain":[7],"momentum,":[8],"technology":[9,57],"solutions":[10],"that":[11],"provide":[12,18],"higher":[13,28],"on-die":[14],"memory":[15],"capacity/bandwidth":[16],"can":[17],"scalability":[19],"beyond":[20],"SRAM.":[21],"Resistive":[22],"RAM":[23],"(RRAM)":[24],"owing":[25],"(1)":[27,77],"bit-density":[29],"(2-4\u00d7":[30],"of":[31,53,84],"SRAM),":[32],"(2)":[33,104],"CMOS":[34],"process/voltage":[35],"compatibility,":[36],"(3)":[37,130],"nano-second":[38],"read":[39],"(RD)":[40],"and":[41,60,124,140,143],"(4)":[42,144],"non-volatility":[43],"has":[44],"emerged":[45],"as":[46,93],"a":[47,72,78,98,150],"promising":[48],"candidate":[49],"[1].":[50,68],"In":[51],"spite":[52],"early":[54],"prototypes,":[55],"several":[56],"challenges":[58],"remain,":[59],"need":[61],"be":[63],"addressed":[64],"through":[65,136],"circuit-technology":[66],"co-design":[67],"This":[69],"paper":[70],"presents":[71],"64Kb":[73],"RRAM":[74,134],"macro":[75],"supporting:":[76],"programmable":[79],"(1":[80],"9)":[82],"number":[83],"row-accesses":[85],"(N)":[86],"enable":[88,149],"vector-matrix":[89],"multiplication":[90],"(referred":[91],"compute-in-memory,":[94],"or":[95],"CIM)":[96],"for":[97,116],"target":[99],"algorithm-level":[100],"inference-accuracy":[101],"[2]":[102],"-[8],":[103],"voltage-based":[105],"RD":[106],"with":[107],"active":[108],"feedback,":[109],"advancing":[110],"the":[111,117,121],"state-of-the-art":[112],"current-based":[113],"RD,":[114],"targeted":[115],"low":[118],"ratio":[119],"between":[120],"high-resistance-state":[122],"(HRS)":[123],"low-resistance-state":[125],"(LRS)":[126],"in":[127],"typical":[128],"RRAM,":[129],"RD-disturb":[131,138],"tolerance":[132],"under":[133],"drift,":[135],"embedded":[137],"monitor":[139],"write":[141],"(WR)-back":[142],"in-situ":[145],"WR":[146],"verification":[147],"tight":[151],"resistance":[152],"distribution.":[153]},"counts_by_year":[{"year":2025,"cited_by_count":13},{"year":2024,"cited_by_count":14},{"year":2023,"cited_by_count":16},{"year":2022,"cited_by_count":29},{"year":2021,"cited_by_count":10}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}