{"id":"https://openalex.org/W3133845769","doi":"https://doi.org/10.1109/isscc42613.2021.9365821","title":"29.5 A 0.008mm<sup>2</sup> 1.5mW 0.625-to-200MHz Fractional Output Divider with 120fs<sub>rms</sub> Jitter Based on Replica-DTC-Free Background Calibration","display_name":"29.5 A 0.008mm<sup>2</sup> 1.5mW 0.625-to-200MHz Fractional Output Divider with 120fs<sub>rms</sub> Jitter Based on Replica-DTC-Free Background Calibration","publication_year":2021,"publication_date":"2021-02-13","ids":{"openalex":"https://openalex.org/W3133845769","doi":"https://doi.org/10.1109/isscc42613.2021.9365821","mag":"3133845769"},"language":"en","primary_location":{"id":"doi:10.1109/isscc42613.2021.9365821","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isscc42613.2021.9365821","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2021 IEEE International Solid- State Circuits Conference (ISSCC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5002476065","display_name":"Chun\u2010Yu Lin","orcid":"https://orcid.org/0000-0003-3375-520X"},"institutions":[{"id":"https://openalex.org/I16733864","display_name":"National Taiwan University","ror":"https://ror.org/05bqach95","country_code":"TW","type":"education","lineage":["https://openalex.org/I16733864"]}],"countries":["TW"],"is_corresponding":true,"raw_author_name":"Chun-Yu Lin","raw_affiliation_strings":["National Taiwan University, Taipei, Taiwan"],"affiliations":[{"raw_affiliation_string":"National Taiwan University, Taipei, Taiwan","institution_ids":["https://openalex.org/I16733864"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5106407198","display_name":"Yu-Ting Hung","orcid":"https://orcid.org/0009-0004-3676-9978"},"institutions":[{"id":"https://openalex.org/I16733864","display_name":"National Taiwan University","ror":"https://ror.org/05bqach95","country_code":"TW","type":"education","lineage":["https://openalex.org/I16733864"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Yu-Ting Hung","raw_affiliation_strings":["National Taiwan University, Taipei, Taiwan"],"affiliations":[{"raw_affiliation_string":"National Taiwan University, Taipei, Taiwan","institution_ids":["https://openalex.org/I16733864"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5091079838","display_name":"Tun-Ju Wang","orcid":null},"institutions":[{"id":"https://openalex.org/I16733864","display_name":"National Taiwan University","ror":"https://ror.org/05bqach95","country_code":"TW","type":"education","lineage":["https://openalex.org/I16733864"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Tun-Ju Wang","raw_affiliation_strings":["National Taiwan University, Taipei, Taiwan"],"affiliations":[{"raw_affiliation_string":"National Taiwan University, Taipei, Taiwan","institution_ids":["https://openalex.org/I16733864"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5027314134","display_name":"Tsung\u2010Hsien Lin","orcid":"https://orcid.org/0000-0002-1733-5945"},"institutions":[{"id":"https://openalex.org/I16733864","display_name":"National Taiwan University","ror":"https://ror.org/05bqach95","country_code":"TW","type":"education","lineage":["https://openalex.org/I16733864"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Tsung-Hsien Lin","raw_affiliation_strings":["National Taiwan University, Taipei, Taiwan"],"affiliations":[{"raw_affiliation_string":"National Taiwan University, Taipei, Taiwan","institution_ids":["https://openalex.org/I16733864"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5002476065"],"corresponding_institution_ids":["https://openalex.org/I16733864"],"apc_list":null,"apc_paid":null,"fwci":0.5054,"has_fulltext":false,"cited_by_count":8,"citation_normalized_percentile":{"value":0.62848328,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":91,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"412","last_page":"414"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10299","display_name":"Photonic and Optical Devices","score":0.9980000257492065,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.8742203712463379},{"id":"https://openalex.org/keywords/dither","display_name":"Dither","score":0.8049039840698242},{"id":"https://openalex.org/keywords/replica","display_name":"Replica","score":0.664584755897522},{"id":"https://openalex.org/keywords/frequency-divider","display_name":"Frequency divider","score":0.5840128660202026},{"id":"https://openalex.org/keywords/direct-digital-synthesizer","display_name":"Direct digital synthesizer","score":0.5794304013252258},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.558885931968689},{"id":"https://openalex.org/keywords/quantization","display_name":"Quantization (signal processing)","score":0.5441251397132874},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.48044630885124207},{"id":"https://openalex.org/keywords/calibration","display_name":"Calibration","score":0.48044535517692566},{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.4325261116027832},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.3113049864768982},{"id":"https://openalex.org/keywords/frequency-synthesizer","display_name":"Frequency synthesizer","score":0.2811659574508667},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2438003122806549},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.1615547239780426},{"id":"https://openalex.org/keywords/noise-shaping","display_name":"Noise shaping","score":0.1057690978050232},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.0849560797214508}],"concepts":[{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.8742203712463379},{"id":"https://openalex.org/C70451592","wikidata":"https://www.wikidata.org/wiki/Q376493","display_name":"Dither","level":3,"score":0.8049039840698242},{"id":"https://openalex.org/C2775937380","wikidata":"https://www.wikidata.org/wiki/Q1232589","display_name":"Replica","level":2,"score":0.664584755897522},{"id":"https://openalex.org/C74982907","wikidata":"https://www.wikidata.org/wiki/Q1455624","display_name":"Frequency divider","level":3,"score":0.5840128660202026},{"id":"https://openalex.org/C166089067","wikidata":"https://www.wikidata.org/wiki/Q1227465","display_name":"Direct digital synthesizer","level":5,"score":0.5794304013252258},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.558885931968689},{"id":"https://openalex.org/C28855332","wikidata":"https://www.wikidata.org/wiki/Q198099","display_name":"Quantization (signal processing)","level":2,"score":0.5441251397132874},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.48044630885124207},{"id":"https://openalex.org/C165838908","wikidata":"https://www.wikidata.org/wiki/Q736777","display_name":"Calibration","level":2,"score":0.48044535517692566},{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.4325261116027832},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.3113049864768982},{"id":"https://openalex.org/C182099602","wikidata":"https://www.wikidata.org/wiki/Q2660678","display_name":"Frequency synthesizer","level":4,"score":0.2811659574508667},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2438003122806549},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.1615547239780426},{"id":"https://openalex.org/C9083635","wikidata":"https://www.wikidata.org/wiki/Q2133535","display_name":"Noise shaping","level":2,"score":0.1057690978050232},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.0849560797214508},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isscc42613.2021.9365821","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isscc42613.2021.9365821","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2021 IEEE International Solid- State Circuits Conference (ISSCC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.6700000166893005}],"awards":[],"funders":[{"id":"https://openalex.org/F4320323900","display_name":"National Taiwan University","ror":"https://ror.org/05bqach95"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":3,"referenced_works":["https://openalex.org/W2057579915","https://openalex.org/W2801331088","https://openalex.org/W2921351625"],"related_works":["https://openalex.org/W3145870900","https://openalex.org/W2350523680","https://openalex.org/W2379961307","https://openalex.org/W2353586717","https://openalex.org/W2347235883","https://openalex.org/W2017031079","https://openalex.org/W2382465025","https://openalex.org/W2323690069","https://openalex.org/W2110035284","https://openalex.org/W2376421545"],"abstract_inverted_index":{"A":[0],"compact,":[1],"low-power,":[2],"low-jitter":[3],"clock":[4],"system":[5],"supporting":[6],"multiple":[7,20,42],"output":[8,31],"frequencies":[9,21],"is":[10,51,63,78],"required":[11],"in":[12,108],"many":[13],"applications.":[14],"Using":[15],"several":[16],"PLLs":[17],"to":[18,40,65,72,84,94,115],"generate":[19,41],"consumes":[22],"large":[23,116],"power":[24,105,117],"and":[25,81,106,118,127],"chip":[26],"area":[27,107,119],"[1].":[28],"Alternatively,":[29],"fractional":[30,49],"dividers":[32],"(FODs)":[33],"can":[34],"be":[35],"employed":[36],"(Fig.":[37],"29.1.5,":[38],"top)":[39],"outputs":[43],"[2]-[5].":[44],"In":[45],"an":[46,109],"FOD,":[47],"the":[48,68,75,86,96],"division":[50],"realized":[52],"by":[53],"dithering":[54],"a":[55],"multi-modulus":[56],"divider":[57],"(MMD).":[58],"The":[59],"digital-to-time":[60],"converter":[61],"(DTC)":[62],"used":[64],"compensate":[66],"for":[67],"quantization":[69],"error":[70],"due":[71],"dithering.":[73],"However,":[74],"DTC":[76,97,102],"characteristic":[77],"PVT":[79],"sensitive":[80],"requires":[82],"calibration":[83,99],"mitigate":[85],"variation.":[87],"Prior":[88],"work":[89],"adopted":[90],"additional":[91],"replica":[92,126],"DTCs":[93,113,129],"realize":[95],"gain":[98],"[2].":[100],"Since":[101],"often":[103],"dominates":[104],"FOD":[110,131],"design,":[111],"extra":[112],"lead":[114],"penalties":[120],"[2],":[121],"[3].":[122],"Furthermore,":[123],"mismatch":[124],"among":[125],"main":[128],"degrades":[130],"performance.":[132]},"counts_by_year":[{"year":2026,"cited_by_count":2},{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":2},{"year":2023,"cited_by_count":3}],"updated_date":"2026-03-18T14:38:29.013473","created_date":"2025-10-10T00:00:00"}