{"id":"https://openalex.org/W2921623970","doi":"https://doi.org/10.1109/isscc.2019.8662526","title":"19.5 Digital Leakage Compensation for a Low-Power and Low-Jitter 0.5-to-5GHz PLL in 10nm FinFET CMOS Technology","display_name":"19.5 Digital Leakage Compensation for a Low-Power and Low-Jitter 0.5-to-5GHz PLL in 10nm FinFET CMOS Technology","publication_year":2019,"publication_date":"2019-02-01","ids":{"openalex":"https://openalex.org/W2921623970","doi":"https://doi.org/10.1109/isscc.2019.8662526","mag":"2921623970"},"language":"en","primary_location":{"id":"doi:10.1109/isscc.2019.8662526","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isscc.2019.8662526","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 IEEE International Solid- State Circuits Conference - (ISSCC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5018623391","display_name":"Y. Fan","orcid":"https://orcid.org/0000-0001-5914-2765"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Yongping Fan","raw_affiliation_strings":["Intel, Hillsboro, OR"],"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102022205","display_name":"Bo Xiang","orcid":"https://orcid.org/0000-0003-1828-2088"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Bo Xiang","raw_affiliation_strings":["Intel, Hillsboro, OR"],"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102737856","display_name":"Dan Zhang","orcid":"https://orcid.org/0000-0002-5700-2969"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Dan Zhang","raw_affiliation_strings":["Intel, Hillsboro, OR"],"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5022406123","display_name":"James Ayers","orcid":"https://orcid.org/0000-0001-9801-3384"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"James S. Ayers","raw_affiliation_strings":["Intel, Hillsboro, OR"],"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102873292","display_name":"Kuan-Yueh James Shen","orcid":"https://orcid.org/0000-0003-2796-2683"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Kuan-Yueh James Shen","raw_affiliation_strings":["Intel, Hillsboro, OR"],"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5085753150","display_name":"Andrey V. Mezhiba","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Andrey Mezhiba","raw_affiliation_strings":["Intel, Hillsboro, OR"],"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5018623391"],"corresponding_institution_ids":["https://openalex.org/I1343180700"],"apc_list":null,"apc_paid":null,"fwci":1.9076,"has_fulltext":false,"cited_by_count":18,"citation_normalized_percentile":{"value":0.8605349,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":94,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"320","last_page":"322"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.8258273005485535},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.8128057718276978},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.6829413771629333},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6056186556816101},{"id":"https://openalex.org/keywords/leakage","display_name":"Leakage (economics)","score":0.5661834478378296},{"id":"https://openalex.org/keywords/phase-noise","display_name":"Phase noise","score":0.5515800714492798},{"id":"https://openalex.org/keywords/low-power-electronics","display_name":"Low-power electronics","score":0.4794972538948059},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.4364873766899109},{"id":"https://openalex.org/keywords/pll-multibit","display_name":"PLL multibit","score":0.4309673607349396},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.4301242232322693},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.3716912567615509},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.2634158134460449},{"id":"https://openalex.org/keywords/power-consumption","display_name":"Power consumption","score":0.2132289707660675},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.11702963709831238}],"concepts":[{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.8258273005485535},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.8128057718276978},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.6829413771629333},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6056186556816101},{"id":"https://openalex.org/C2777042071","wikidata":"https://www.wikidata.org/wiki/Q6509304","display_name":"Leakage (economics)","level":2,"score":0.5661834478378296},{"id":"https://openalex.org/C89631360","wikidata":"https://www.wikidata.org/wiki/Q1428766","display_name":"Phase noise","level":2,"score":0.5515800714492798},{"id":"https://openalex.org/C117551214","wikidata":"https://www.wikidata.org/wiki/Q6692774","display_name":"Low-power electronics","level":4,"score":0.4794972538948059},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.4364873766899109},{"id":"https://openalex.org/C77881186","wikidata":"https://www.wikidata.org/wiki/Q7119642","display_name":"PLL multibit","level":4,"score":0.4309673607349396},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.4301242232322693},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.3716912567615509},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.2634158134460449},{"id":"https://openalex.org/C2984118289","wikidata":"https://www.wikidata.org/wiki/Q29954","display_name":"Power consumption","level":3,"score":0.2132289707660675},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.11702963709831238},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C139719470","wikidata":"https://www.wikidata.org/wiki/Q39680","display_name":"Macroeconomics","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isscc.2019.8662526","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isscc.2019.8662526","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 IEEE International Solid- State Circuits Conference - (ISSCC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.8899999856948853}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W2111478398","https://openalex.org/W2112008043","https://openalex.org/W2145015226","https://openalex.org/W2172440946","https://openalex.org/W2288499521","https://openalex.org/W2593145514","https://openalex.org/W4242161270","https://openalex.org/W6676844732","https://openalex.org/W6681013964"],"related_works":["https://openalex.org/W2474043983","https://openalex.org/W2374354148","https://openalex.org/W2544336511","https://openalex.org/W2078513307","https://openalex.org/W1994021281","https://openalex.org/W2566880546","https://openalex.org/W1978186604","https://openalex.org/W2943997861","https://openalex.org/W2144737022","https://openalex.org/W2143576345"],"abstract_inverted_index":{"As":[0],"the":[1,15,20,30,33,40,66,79,127],"push":[2],"for":[3,126],"low-power,":[4],"low-jitter,":[5],"and":[6,18,39,55,74,99,106],"low-area":[7],"phase-locked":[8],"loop":[9],"(PLL)":[10],"design":[11],"[1]":[12],"continues":[13],"in":[14,29,82,130],"10nm":[16],"node":[17],"beyond,":[19],"leakage":[21,60,80,128],"from":[22],"various":[23],"sources":[24],"could":[25],"become":[26],"an":[27],"issue":[28],"applications":[31],"where":[32],"reference":[34,75],"clock":[35],"frequency":[36],"is":[37,44,141],"low":[38,147],"static":[41,69],"phase":[42,70,148],"error":[43,149],"required":[45],"to":[46,49,103,117,121,143],"be":[47],"close":[48],"zero":[50,145],"at":[51],"all":[52],"process":[53],"corners":[54],"temperatures.":[56],"The":[57],"impacts":[58],"of":[59,68],"currents":[61],"on":[62],"analog":[63,83,131,133],"PLLs":[64,87],"are":[65,136],"increase":[67],"error,":[71],"higher":[72,96,100],"jitter":[73,101],"spur.":[76],"To":[77,124],"mitigate":[78],"sensitivity":[81,120],"PLL":[84],"designs,":[85],"digital":[86],"have":[88],"been":[89],"designed":[90],"[2-3],":[91],"but":[92,139],"they":[93],"often":[94],"exhibit":[95],"power":[97],"consumption":[98],"due":[102,116],"quantization":[104],"noise,":[105],"require":[107],"high-performance":[108],"voltage":[109],"regulators":[110],"or":[111,146],"supply-noise":[112],"cancellation":[113],"techniques":[114],"[4]":[115],"their":[118],"high":[119],"power-supply":[122],"noise.":[123],"compensate":[125],"current":[129],"PLLs,":[132],"compensation":[134],"circuits":[135],"proposed":[137],"[5-6],":[138],"it":[140],"impossible":[142],"achieve":[144],"across":[150],"PVT":[151],"corners.":[152]},"counts_by_year":[{"year":2023,"cited_by_count":2},{"year":2022,"cited_by_count":3},{"year":2021,"cited_by_count":7},{"year":2020,"cited_by_count":4},{"year":2019,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}