{"id":"https://openalex.org/W2921351161","doi":"https://doi.org/10.1109/isscc.2019.8662393","title":"13.2 A 3.6Mb 10.1Mb/mm<sup>2</sup> Embedded Non-Volatile ReRAM Macro in 22nm FinFET Technology with Adaptive Forming/Set/Reset Schemes Yielding Down to 0.5V with Sensing Time of 5ns at 0.7V","display_name":"13.2 A 3.6Mb 10.1Mb/mm<sup>2</sup> Embedded Non-Volatile ReRAM Macro in 22nm FinFET Technology with Adaptive Forming/Set/Reset Schemes Yielding Down to 0.5V with Sensing Time of 5ns at 0.7V","publication_year":2019,"publication_date":"2019-02-01","ids":{"openalex":"https://openalex.org/W2921351161","doi":"https://doi.org/10.1109/isscc.2019.8662393","mag":"2921351161"},"language":"en","primary_location":{"id":"doi:10.1109/isscc.2019.8662393","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isscc.2019.8662393","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 IEEE International Solid- State Circuits Conference - (ISSCC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5023812483","display_name":"Pulkit Jain","orcid":"https://orcid.org/0000-0001-5708-9761"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Pulkit Jain","raw_affiliation_strings":["Intel, Hillsboro, OR"],"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101505370","display_name":"\u00dcm\u00fct Arslan","orcid":"https://orcid.org/0000-0002-0884-8079"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Umut Arslan","raw_affiliation_strings":["Intel, Hillsboro, OR"],"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5052894056","display_name":"Meenakshi Sekhar","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Meenakshi Sekhar","raw_affiliation_strings":["Intel, Hillsboro, OR"],"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5025781381","display_name":"Blake C. Lin","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Blake C. Lin","raw_affiliation_strings":["Intel, Hillsboro, OR"],"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101012313","display_name":"Liqiong Wei","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Liqiong Wei","raw_affiliation_strings":["Intel, Hillsboro, OR"],"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5067247092","display_name":"Tanaya Sahu","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Tanaya Sahu","raw_affiliation_strings":["Intel, Hillsboro, OR"],"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5086560263","display_name":"Juan Alzate-vinasco","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Juan Alzate-vinasco","raw_affiliation_strings":["Intel, Hillsboro, OR"],"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5062506535","display_name":"Ajay Vangapaty","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ajay Vangapaty","raw_affiliation_strings":["Intel, Hillsboro, OR"],"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5027957128","display_name":"Mesut Meterelliyoz","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Mesut Meterelliyoz","raw_affiliation_strings":["Intel, Hillsboro, OR"],"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5019726807","display_name":"Nathan Strutt","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Nathan Strutt","raw_affiliation_strings":["Intel, Hillsboro, OR"],"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5018350763","display_name":"Albert B. Chen","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Albert B. Chen","raw_affiliation_strings":["Intel, Hillsboro, OR"],"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5071953440","display_name":"P. Hentges","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Patrick Hentges","raw_affiliation_strings":["Intel, Hillsboro, OR"],"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5085566412","display_name":"Pedro A. Quintero","orcid":"https://orcid.org/0000-0003-2039-4003"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Pedro A. Quintero","raw_affiliation_strings":["Intel, Hillsboro, OR"],"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5056145942","display_name":"Chris Connor","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Chris Connor","raw_affiliation_strings":["Intel, Hillsboro, OR"],"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5059652627","display_name":"O. Golonzka","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Oleg Golonzka","raw_affiliation_strings":["Intel, Hillsboro, OR"],"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5112197631","display_name":"Kevin Fischer","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Kevin Fischer","raw_affiliation_strings":["Intel, Hillsboro, OR"],"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5063387912","display_name":"Fatih Hamzaoglu","orcid":"https://orcid.org/0000-0003-3500-5007"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Fatih Hamzaoglu","raw_affiliation_strings":["Intel, Hillsboro, OR"],"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":17,"corresponding_author_ids":["https://openalex.org/A5023812483"],"corresponding_institution_ids":["https://openalex.org/I1343180700"],"apc_list":null,"apc_paid":null,"fwci":8.4652,"has_fulltext":false,"cited_by_count":128,"citation_normalized_percentile":{"value":0.98240396,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":99,"max":100},"biblio":{"volume":null,"issue":null,"first_page":"212","last_page":"214"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/resistive-random-access-memory","display_name":"Resistive random-access memory","score":0.8343810439109802},{"id":"https://openalex.org/keywords/reset","display_name":"Reset (finance)","score":0.5284397602081299},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.5198148488998413},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5109013915061951},{"id":"https://openalex.org/keywords/non-volatile-memory","display_name":"Non-volatile memory","score":0.5020177364349365},{"id":"https://openalex.org/keywords/reliability","display_name":"Reliability (semiconductor)","score":0.49519601464271545},{"id":"https://openalex.org/keywords/resistor","display_name":"Resistor","score":0.48168763518333435},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.479233056306839},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.4544743001461029},{"id":"https://openalex.org/keywords/memory-cell","display_name":"Memory cell","score":0.4455380141735077},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.43671706318855286},{"id":"https://openalex.org/keywords/data-retention","display_name":"Data retention","score":0.424172043800354},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.41180047392845154},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.38128596544265747},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.37514743208885193},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.37501174211502075},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.23920267820358276},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.2389344573020935}],"concepts":[{"id":"https://openalex.org/C182019814","wikidata":"https://www.wikidata.org/wiki/Q1143830","display_name":"Resistive random-access memory","level":3,"score":0.8343810439109802},{"id":"https://openalex.org/C2779795794","wikidata":"https://www.wikidata.org/wiki/Q7315343","display_name":"Reset (finance)","level":2,"score":0.5284397602081299},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.5198148488998413},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5109013915061951},{"id":"https://openalex.org/C177950962","wikidata":"https://www.wikidata.org/wiki/Q10997658","display_name":"Non-volatile memory","level":2,"score":0.5020177364349365},{"id":"https://openalex.org/C43214815","wikidata":"https://www.wikidata.org/wiki/Q7310987","display_name":"Reliability (semiconductor)","level":3,"score":0.49519601464271545},{"id":"https://openalex.org/C137488568","wikidata":"https://www.wikidata.org/wiki/Q5321","display_name":"Resistor","level":3,"score":0.48168763518333435},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.479233056306839},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.4544743001461029},{"id":"https://openalex.org/C2776638159","wikidata":"https://www.wikidata.org/wiki/Q18343761","display_name":"Memory cell","level":4,"score":0.4455380141735077},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.43671706318855286},{"id":"https://openalex.org/C2780866740","wikidata":"https://www.wikidata.org/wiki/Q5227345","display_name":"Data retention","level":2,"score":0.424172043800354},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.41180047392845154},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.38128596544265747},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.37514743208885193},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.37501174211502075},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.23920267820358276},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.2389344573020935},{"id":"https://openalex.org/C106159729","wikidata":"https://www.wikidata.org/wiki/Q2294553","display_name":"Financial economics","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isscc.2019.8662393","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isscc.2019.8662393","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 IEEE International Solid- State Circuits Conference - (ISSCC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W1573873562","https://openalex.org/W1602621499","https://openalex.org/W1906827922","https://openalex.org/W2146999254","https://openalex.org/W2581964970","https://openalex.org/W2794194363","https://openalex.org/W6636008171"],"related_works":["https://openalex.org/W4312903428","https://openalex.org/W2621306919","https://openalex.org/W2032785938","https://openalex.org/W1966944787","https://openalex.org/W3185106882","https://openalex.org/W1980301972","https://openalex.org/W2761437135","https://openalex.org/W2086074825","https://openalex.org/W2104937488","https://openalex.org/W1602728803"],"abstract_inverted_index":{"A":[0,107,134],"resistive":[1],"RAM":[2],"(ReRAM)":[3],"macro":[4],"is":[5,86,195],"developed":[6],"as":[7],"a":[8,37,139,184],"low-cost,":[9],"magnetic-disturb-immune":[10],"option":[11],"for":[12,16],"embedded,":[13],"non-volatile":[14],"memory":[15,181],"SoCs":[17],"used":[18,167],"in":[19,36,102,143],"IoT":[20],"and":[21,69,105,109,124,131,138,151,160,174],"automotive":[22],"applications.":[23],"We":[24],"demonstrate":[25],"the":[26,144,148,152,163,178,198],"smallest":[27,78],"ReRAM":[28],"subarray":[29,42],"density":[30],"of":[31,119,147],"10.1Mb/mm":[32],"<sup":[33],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[34,83],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">2</sup>":[35],"22nm":[38],"low-power":[39],"process.":[40],"The":[41,77,180],"uses":[43,70,183],"nominal-gate":[44],"FINFET":[45],"logic":[46],"devices,":[47],"with":[48],"material":[49],"innovations":[50],"to":[51,89,156,169],"allow":[52],"low-voltage":[53],"switching":[54],"without":[55],"impacting":[56],"transistor":[57],"reliability.":[58],"Prior":[59],"art":[60],"features":[61],"larger":[62],"bit":[63],"cell":[64],"size":[65],"or":[66,72],"array":[67],"density,":[68],"28":[71],"40nm":[73],"technology":[74],"nodes":[75],"[1]-[4].":[76],"read-sense":[79],"time":[80],"(t":[81],"<sub":[82],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">SENSE</sub>":[84],"=5ns@0.7V)":[85],"demonstrated,":[87],"compared":[88],"previous":[90],"works":[91],"[2].":[92],"An":[93],"optimized":[94],"pulse-width":[95],"(PW)":[96],"voltage-current":[97],"write-verify-write":[98],"(PVC-WVW)":[99],"sequence":[100],"helps":[101],"mitigating":[103],"endurance":[104,125],"variability.":[106],"flexible":[108],"low-area":[110],"TFR":[111,165],"(thin-film":[112],"resistor)":[113],"based":[114],"reference":[115,140],"scheme":[116],"enables":[117],"optimization":[118],"forming,":[120],"write":[121],"yield,":[122],"retention":[123],"tradeoffs":[126],"by":[127],"skewing":[128],"different":[129],"verify":[130],"read":[132],"resistances.":[133],"temperature-constant":[135],"current":[136,150],"source":[137],"resistance":[141],"help":[142],"precise":[145],"control":[146],"forming/set":[149],"verify/read":[153],"operations.":[154],"Compared":[155],"area-inefficient":[157],"bandgap":[158],"circuits":[159],"temperature":[161],"sensors,":[162],"in-situ":[164,190],"was":[166],"due":[168],"its":[170],"low":[171],"area,":[172],"flexibility":[173],"seamless":[175],"integration":[176],"into":[177],"SoC.":[179],"bank":[182],"single":[185],"supply":[186],"coming":[187],"from":[188],"an":[189],"charge":[191],"pump":[192],"(CP)":[193],"that":[194],"shared":[196],"across":[197],"macro.":[199]},"counts_by_year":[{"year":2025,"cited_by_count":18},{"year":2024,"cited_by_count":17},{"year":2023,"cited_by_count":22},{"year":2022,"cited_by_count":15},{"year":2021,"cited_by_count":23},{"year":2020,"cited_by_count":26},{"year":2019,"cited_by_count":7}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
