{"id":"https://openalex.org/W2789659455","doi":"https://doi.org/10.1109/isscc.2018.8310251","title":"A 23.6Mb/mm<sup>2</sup> SRAM in 10nm FinFET technology with pulsed PMOS TVC and stepped-WL for low-voltage applications","display_name":"A 23.6Mb/mm<sup>2</sup> SRAM in 10nm FinFET technology with pulsed PMOS TVC and stepped-WL for low-voltage applications","publication_year":2018,"publication_date":"2018-02-01","ids":{"openalex":"https://openalex.org/W2789659455","doi":"https://doi.org/10.1109/isscc.2018.8310251","mag":"2789659455"},"language":"en","primary_location":{"id":"doi:10.1109/isscc.2018.8310251","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isscc.2018.8310251","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5007891380","display_name":"Zheng Guo","orcid":"https://orcid.org/0000-0001-8615-9749"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Zheng Guo","raw_affiliation_strings":["Intel, Hillsboro, OR","Intel, Hillsboro, OR#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel, Hillsboro, OR#TAB#","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100644921","display_name":"Daeyeon Kim","orcid":"https://orcid.org/0000-0002-5879-8313"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Daeyeon Kim","raw_affiliation_strings":["Intel, Hillsboro, OR","Intel, Hillsboro, OR#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel, Hillsboro, OR#TAB#","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5050071437","display_name":"Satyanand Nalam","orcid":"https://orcid.org/0000-0002-6767-1752"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Satyanand Nalam","raw_affiliation_strings":["Intel, Hillsboro, OR","Intel, Hillsboro, OR#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel, Hillsboro, OR#TAB#","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5041500446","display_name":"Jami Wiedemer","orcid":"https://orcid.org/0000-0001-6874-0636"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jami Wiedemer","raw_affiliation_strings":["Intel, Hillsboro, OR","Intel, Hillsboro, OR#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel, Hillsboro, OR#TAB#","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100363482","display_name":"Xiaofei Wang","orcid":"https://orcid.org/0000-0003-2178-8661"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Xiaofei Wang","raw_affiliation_strings":["Intel, Hillsboro, OR","Intel, Hillsboro, OR#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel, Hillsboro, OR#TAB#","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5053857493","display_name":"Eric Karl","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Eric Karl","raw_affiliation_strings":["Intel, Hillsboro, OR","Intel, Hillsboro, OR#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel, Hillsboro, OR#TAB#","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I1343180700"],"apc_list":null,"apc_paid":null,"fwci":4.2861,"has_fulltext":false,"cited_by_count":23,"citation_normalized_percentile":{"value":0.95283578,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":90,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"196","last_page":"198"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.7013134956359863},{"id":"https://openalex.org/keywords/pmos-logic","display_name":"PMOS logic","score":0.6574555039405823},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.6207150220870972},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.5489892363548279},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.446354478597641},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.43835383653640747},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.4035753607749939},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.34308677911758423},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.33154550194740295},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.22955003380775452}],"concepts":[{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.7013134956359863},{"id":"https://openalex.org/C27050352","wikidata":"https://www.wikidata.org/wiki/Q173605","display_name":"PMOS logic","level":4,"score":0.6574555039405823},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.6207150220870972},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.5489892363548279},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.446354478597641},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.43835383653640747},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.4035753607749939},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.34308677911758423},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.33154550194740295},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.22955003380775452}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isscc.2018.8310251","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isscc.2018.8310251","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.8899999856948853}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W2008362573","https://openalex.org/W2073818373","https://openalex.org/W2087345965","https://openalex.org/W2096288219","https://openalex.org/W2096890581","https://openalex.org/W2787310733","https://openalex.org/W6672536603"],"related_works":["https://openalex.org/W2730314563","https://openalex.org/W2031972468","https://openalex.org/W4388836178","https://openalex.org/W1510452813","https://openalex.org/W2058541779","https://openalex.org/W1827298495","https://openalex.org/W2006330903","https://openalex.org/W2109746608","https://openalex.org/W2272535745","https://openalex.org/W2262823117"],"abstract_inverted_index":{"The":[0],"emergence":[1],"of":[2,14,23,36,71],"cloud":[3],"computing":[4],"and":[5,25,29,74,105],"big":[6],"data":[7],"analytics,":[8],"accompanied":[9],"by":[10],"a":[11,58,93,102,106],"sustained":[12],"growth":[13],"battery-powered":[15],"mobile":[16],"devices,":[17],"continues":[18,55],"to":[19,56],"drive":[20],"the":[21,37,48,72],"importance":[22],"energy":[24],"area":[26],"efficient":[27],"CPU":[28],"SoC":[30],"designs.":[31],"Low-voltage":[32],"operation":[33],"remains":[34],"one":[35],"primary":[38],"approaches":[39],"for":[40,60,80],"active":[41],"power":[42],"reduction,":[43],"but":[44],"SRAM":[45,63,89],"l/MINcan":[46],"limit":[47],"minimum":[49],"operating":[50],"voltage.":[51],"Device":[52],"size":[53],"quantization":[54],"be":[57],"challenge":[59],"compact":[61],"6T":[62],"design":[64,77],"in":[65,92],"FinFET":[66,100],"technologies,":[67],"where":[68],"careful":[69],"co-optimization":[70],"technology":[73,97],"assist":[75],"circuit":[76],"is":[78],"required":[79],"high-density":[81,103],"low-voltage":[82,107],"array":[83,90],"implementations.":[84],"This":[85],"paper":[86],"presents":[87],"two":[88],"designs":[91],"10nm":[94],"low-power":[95],"CMOS":[96],"featuring":[98],"3rdgeneration":[99],"transistors:":[101],"23.6Mb/mm2array":[104],"20.4Mb/mm2array.":[108]},"counts_by_year":[{"year":2025,"cited_by_count":4},{"year":2024,"cited_by_count":2},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":5},{"year":2021,"cited_by_count":4},{"year":2020,"cited_by_count":4},{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}