{"id":"https://openalex.org/W2793528983","doi":"https://doi.org/10.1109/isscc.2018.8310170","title":"SkyLake-SP: A 14nm 28-Core xeon\u00ae processor","display_name":"SkyLake-SP: A 14nm 28-Core xeon\u00ae processor","publication_year":2018,"publication_date":"2018-02-01","ids":{"openalex":"https://openalex.org/W2793528983","doi":"https://doi.org/10.1109/isscc.2018.8310170","mag":"2793528983"},"language":"en","primary_location":{"id":"doi:10.1109/isscc.2018.8310170","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isscc.2018.8310170","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5036660816","display_name":"Simon Tam","orcid":"https://orcid.org/0000-0003-3918-7100"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Simon M. Tam","raw_affiliation_strings":["Intel, Santa Clara, CA"],"affiliations":[{"raw_affiliation_string":"Intel, Santa Clara, CA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5032763051","display_name":"H. Muljono","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Harry Muljono","raw_affiliation_strings":["Intel, Santa Clara, CA"],"affiliations":[{"raw_affiliation_string":"Intel, Santa Clara, CA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5004393760","display_name":"Min Huang","orcid":"https://orcid.org/0009-0009-5807-054X"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Min Huang","raw_affiliation_strings":["Intel, Santa Clara, CA"],"affiliations":[{"raw_affiliation_string":"Intel, Santa Clara, CA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5084221559","display_name":"S Iyer","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sitaraman Iyer","raw_affiliation_strings":["Intel, Santa Clara, CA"],"affiliations":[{"raw_affiliation_string":"Intel, Santa Clara, CA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5061830358","display_name":"Kalapi Royneogi","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Kalapi Royneogi","raw_affiliation_strings":["Intel, Santa Clara, CA"],"affiliations":[{"raw_affiliation_string":"Intel, Santa Clara, CA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5034744450","display_name":"Nagmohan Satti","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Nagmohan Satti","raw_affiliation_strings":["Intel, Santa Clara, CA"],"affiliations":[{"raw_affiliation_string":"Intel, Santa Clara, CA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5084326971","display_name":"M. Rizwan Jameel Qureshi","orcid":"https://orcid.org/0000-0002-1664-0737"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Rizwan Qureshi","raw_affiliation_strings":["Intel, Santa Clara, CA"],"affiliations":[{"raw_affiliation_string":"Intel, Santa Clara, CA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100344362","display_name":"Wei Chen","orcid":"https://orcid.org/0000-0001-9550-0523"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Wei Chen","raw_affiliation_strings":["Intel, Santa Clara, CA"],"affiliations":[{"raw_affiliation_string":"Intel, Santa Clara, CA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5068373833","display_name":"Tom Wang","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Tom Wang","raw_affiliation_strings":["Intel, Santa Clara, CA"],"affiliations":[{"raw_affiliation_string":"Intel, Santa Clara, CA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5017033706","display_name":"Hubert Hsieh","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Hubert Hsieh","raw_affiliation_strings":["Intel, Santa Clara, CA"],"affiliations":[{"raw_affiliation_string":"Intel, Santa Clara, CA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5108618300","display_name":"Sujal Vora","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sujal Vora","raw_affiliation_strings":["Intel, Santa Clara, CA"],"affiliations":[{"raw_affiliation_string":"Intel, Santa Clara, CA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5102956843","display_name":"Eddie Wang","orcid":"https://orcid.org/0000-0002-9814-0102"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Eddie Wang","raw_affiliation_strings":["Intel, Santa Clara, CA"],"affiliations":[{"raw_affiliation_string":"Intel, Santa Clara, CA","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":12,"corresponding_author_ids":["https://openalex.org/A5036660816"],"corresponding_institution_ids":["https://openalex.org/I1343180700"],"apc_list":null,"apc_paid":null,"fwci":7.3216,"has_fulltext":false,"cited_by_count":49,"citation_normalized_percentile":{"value":0.97763383,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":96,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"34","last_page":"36"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9983999729156494,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/pci-express","display_name":"PCI Express","score":0.8544347286224365},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6682803630828857},{"id":"https://openalex.org/keywords/xeon","display_name":"Xeon","score":0.6217860579490662},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5897908806800842},{"id":"https://openalex.org/keywords/xeon-phi","display_name":"Xeon Phi","score":0.5726116895675659},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.5011389255523682},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.4669877886772156},{"id":"https://openalex.org/keywords/code","display_name":"Code (set theory)","score":0.4545454680919647},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.39589160680770874},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.19995802640914917}],"concepts":[{"id":"https://openalex.org/C64270927","wikidata":"https://www.wikidata.org/wiki/Q206924","display_name":"PCI Express","level":3,"score":0.8544347286224365},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6682803630828857},{"id":"https://openalex.org/C145108525","wikidata":"https://www.wikidata.org/wiki/Q656154","display_name":"Xeon","level":2,"score":0.6217860579490662},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5897908806800842},{"id":"https://openalex.org/C96972482","wikidata":"https://www.wikidata.org/wiki/Q1049168","display_name":"Xeon Phi","level":2,"score":0.5726116895675659},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.5011389255523682},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.4669877886772156},{"id":"https://openalex.org/C2776760102","wikidata":"https://www.wikidata.org/wiki/Q5139990","display_name":"Code (set theory)","level":3,"score":0.4545454680919647},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.39589160680770874},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.19995802640914917},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isscc.2018.8310170","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isscc.2018.8310170","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.7799999713897705,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W1966797259","https://openalex.org/W1999903189","https://openalex.org/W2018960859","https://openalex.org/W2288669328","https://openalex.org/W6650237341"],"related_works":["https://openalex.org/W1974923383","https://openalex.org/W2475524688","https://openalex.org/W2739740241","https://openalex.org/W2085105049","https://openalex.org/W2526069705","https://openalex.org/W2024016913","https://openalex.org/W2019153376","https://openalex.org/W2981664121","https://openalex.org/W2022666014","https://openalex.org/W2032784242"],"abstract_inverted_index":{"SkyLake-SP":[0],"(Scalable":[1],"Performance),":[2],"code":[3],"name":[4],"SKX,":[5],"is":[6,36],"the":[7,15,67,108,114,118],"next":[8],"generation":[9],"Xeon\u00ae":[10],"server":[11],"processor":[12,27,69],"fabricated":[13],"on":[14],"Intel\u00ae":[16],"14nm":[17],"tri-gate":[18],"CMOS":[19],"technology":[20],"with":[21],"11-metal":[22],"layers":[23],"[1,2].":[24],"The":[25],"SKX":[26,34,68,85,119],"family":[28],"has":[29],"three":[30],"core-count":[31],"configurations.":[32],"Each":[33],"core":[35],"accompanied":[37],"by":[38,91],"1MB":[39],"of":[40,51,64,117],"dedicated":[41],"L2":[42],"(2":[43],"<sup":[44,55],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[45,56],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">nd</sup>":[46],"level":[47,58],"cache)":[48],"and":[49,80],"1.375MB":[50],"non-exclusive":[52],"L3":[53],"(3":[54],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">rd</sup>":[57],"cache).":[59],"At":[60],"its":[61],"maximum":[62],"configuration":[63],"28":[65],"cores,":[66],"supports":[70,86],"6":[71],"DDR4":[72],"channels":[73],"(2666MT/s),":[74],"3\u00d720-lanes":[75],"UPI":[76],"processor-to-processor":[77],"links":[78,83],"(10.4GT/s)":[79],"x48+4":[81],"PCIE":[82],"(8GT/s).":[84],"per-core":[87],"power-performance":[88],"optimization":[89],"enabled":[90],"on-die":[92,103,109],"integrated":[93],"voltage":[94],"regulators":[95],"(FIVR)":[96],"[3,":[97],"4].":[98],"A":[99],"new":[100],"2-dimensional":[101],"synchronous":[102],"MESH":[104],"fabric":[105],"interconnects":[106],"all":[107],"components.":[110],"Fig.":[111],"2.1.1":[112],"shows":[113],"overall":[115],"architecture":[116],"processor.":[120]},"counts_by_year":[{"year":2025,"cited_by_count":4},{"year":2024,"cited_by_count":4},{"year":2023,"cited_by_count":6},{"year":2022,"cited_by_count":6},{"year":2021,"cited_by_count":7},{"year":2020,"cited_by_count":9},{"year":2019,"cited_by_count":10},{"year":2018,"cited_by_count":3}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}