{"id":"https://openalex.org/W2592428089","doi":"https://doi.org/10.1109/isscc.2017.7870257","title":"3.3 A 14nm 1GHz FPGA with 2.5D transceiver integration","display_name":"3.3 A 14nm 1GHz FPGA with 2.5D transceiver integration","publication_year":2017,"publication_date":"2017-02-01","ids":{"openalex":"https://openalex.org/W2592428089","doi":"https://doi.org/10.1109/isscc.2017.7870257","mag":"2592428089"},"language":"en","primary_location":{"id":"doi:10.1109/isscc.2017.7870257","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isscc.2017.7870257","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 IEEE International Solid-State Circuits Conference (ISSCC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5007361879","display_name":"David Greenhill","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"David Greenhill","raw_affiliation_strings":["Intel, San Jose, CA"],"affiliations":[{"raw_affiliation_string":"Intel, San Jose, CA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103340910","display_name":"Ron Ho","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ron Ho","raw_affiliation_strings":["Intel, San Jose, CA"],"affiliations":[{"raw_affiliation_string":"Intel, San Jose, CA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102968798","display_name":"David Lewis","orcid":"https://orcid.org/0000-0002-8126-5662"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"David Lewis","raw_affiliation_strings":["Intel, Toronto, Canada"],"affiliations":[{"raw_affiliation_string":"Intel, Toronto, Canada","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5078387900","display_name":"Herman Schmit","orcid":"https://orcid.org/0000-0002-0109-7604"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Herman Schmit","raw_affiliation_strings":["Intel, San Jose, CA"],"affiliations":[{"raw_affiliation_string":"Intel, San Jose, CA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5051319851","display_name":"Kok Hong Chan","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Kok Hong Chan","raw_affiliation_strings":["Intel, San Jose, CA"],"affiliations":[{"raw_affiliation_string":"Intel, San Jose, CA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5075659039","display_name":"Tong Andy","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Andy Tong","raw_affiliation_strings":["Intel, San Jose, CA"],"affiliations":[{"raw_affiliation_string":"Intel, San Jose, CA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5091883777","display_name":"Sean Atsatt","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sean Atsatt","raw_affiliation_strings":["Intel, San Jose, CA"],"affiliations":[{"raw_affiliation_string":"Intel, San Jose, CA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5031787837","display_name":"Dana How","orcid":"https://orcid.org/0000-0003-2843-1972"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Dana How","raw_affiliation_strings":["Intel, San Jose, CA"],"affiliations":[{"raw_affiliation_string":"Intel, San Jose, CA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5071641540","display_name":"McElheny Peter","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Peter McElheny","raw_affiliation_strings":["Intel, San Jose, CA"],"affiliations":[{"raw_affiliation_string":"Intel, San Jose, CA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5037236761","display_name":"Duwel Keith","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Keith Duwel","raw_affiliation_strings":["Intel, San Jose, CA"],"affiliations":[{"raw_affiliation_string":"Intel, San Jose, CA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5039740312","display_name":"Schulz Jeffrey","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jeffrey Schulz","raw_affiliation_strings":["Intel, San Jose, CA"],"affiliations":[{"raw_affiliation_string":"Intel, San Jose, CA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5029071897","display_name":"Faulkner Darren","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Darren Faulkner","raw_affiliation_strings":["Intel, Austin, TX"],"affiliations":[{"raw_affiliation_string":"Intel, Austin, TX","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111986987","display_name":"G. Iyer","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Gopal Iyer","raw_affiliation_strings":["Intel, San Jose, CA, United States of America"],"affiliations":[{"raw_affiliation_string":"Intel, San Jose, CA, United States of America","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5060783478","display_name":"George Chen","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"George Chen","raw_affiliation_strings":["Intel, San Jose, CA"],"affiliations":[{"raw_affiliation_string":"Intel, San Jose, CA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5006713716","display_name":"Hee Kong Phoon","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Hee Kong Phoon","raw_affiliation_strings":["Intel, Penang, Malaysia"],"affiliations":[{"raw_affiliation_string":"Intel, Penang, Malaysia","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5016058460","display_name":"Han Wooi Lim","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Han Wooi Lim","raw_affiliation_strings":["Intel, Penang, Malaysia"],"affiliations":[{"raw_affiliation_string":"Intel, Penang, Malaysia","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5069283935","display_name":"Wei-Yee Koay","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Wei-Yee Koay","raw_affiliation_strings":["Intel, Penang, Malaysia"],"affiliations":[{"raw_affiliation_string":"Intel, Penang, Malaysia","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5073122240","display_name":"Ty Garibay","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ty Garibay","raw_affiliation_strings":["Intel, Austin, TX"],"affiliations":[{"raw_affiliation_string":"Intel, Austin, TX","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":18,"corresponding_author_ids":["https://openalex.org/A5007361879"],"corresponding_institution_ids":["https://openalex.org/I1343180700"],"apc_list":null,"apc_paid":null,"fwci":6.9481,"has_fulltext":false,"cited_by_count":53,"citation_normalized_percentile":{"value":0.97810808,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":90,"max":99},"biblio":{"volume":"2017","issue":null,"first_page":"54","last_page":"55"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/transceiver","display_name":"Transceiver","score":0.8798683881759644},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8459604978561401},{"id":"https://openalex.org/keywords/modular-design","display_name":"Modular design","score":0.6647437214851379},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6603518724441528},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.6082652807235718},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.5444156527519226},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5427671670913696},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.5241753458976746},{"id":"https://openalex.org/keywords/microprocessor","display_name":"Microprocessor","score":0.5164949893951416},{"id":"https://openalex.org/keywords/gate-array","display_name":"Gate array","score":0.5041571855545044},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.4751165509223938},{"id":"https://openalex.org/keywords/programmable-logic-array","display_name":"Programmable logic array","score":0.46811121702194214},{"id":"https://openalex.org/keywords/dice","display_name":"Dice","score":0.46490204334259033},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.2100832164287567},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.18435990810394287},{"id":"https://openalex.org/keywords/wireless","display_name":"Wireless","score":0.09515509009361267}],"concepts":[{"id":"https://openalex.org/C7720470","wikidata":"https://www.wikidata.org/wiki/Q954187","display_name":"Transceiver","level":3,"score":0.8798683881759644},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8459604978561401},{"id":"https://openalex.org/C101468663","wikidata":"https://www.wikidata.org/wiki/Q1620158","display_name":"Modular design","level":2,"score":0.6647437214851379},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6603518724441528},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.6082652807235718},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.5444156527519226},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5427671670913696},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.5241753458976746},{"id":"https://openalex.org/C2780728072","wikidata":"https://www.wikidata.org/wiki/Q5297","display_name":"Microprocessor","level":2,"score":0.5164949893951416},{"id":"https://openalex.org/C114237110","wikidata":"https://www.wikidata.org/wiki/Q114901","display_name":"Gate array","level":3,"score":0.5041571855545044},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.4751165509223938},{"id":"https://openalex.org/C182322920","wikidata":"https://www.wikidata.org/wiki/Q2112217","display_name":"Programmable logic array","level":3,"score":0.46811121702194214},{"id":"https://openalex.org/C22029948","wikidata":"https://www.wikidata.org/wiki/Q45089","display_name":"Dice","level":2,"score":0.46490204334259033},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.2100832164287567},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.18435990810394287},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.09515509009361267},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/isscc.2017.7870257","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isscc.2017.7870257","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 IEEE International Solid-State Circuits Conference (ISSCC)","raw_type":"proceedings-article"},{"id":"mag:2746766309","is_oa":false,"landing_page_url":"http://jglobal.jst.go.jp/en/public/20090422/201702237092750773","pdf_url":null,"source":{"id":"https://openalex.org/S4306512817","display_name":"IEEE Conference Proceedings","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":null,"raw_source_name":"IEEE Conference Proceedings","raw_type":null}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":4,"referenced_works":["https://openalex.org/W2092421293","https://openalex.org/W2264331490","https://openalex.org/W2277819611","https://openalex.org/W2518432791"],"related_works":["https://openalex.org/W2014165129","https://openalex.org/W4309935840","https://openalex.org/W2046817858","https://openalex.org/W2052520871","https://openalex.org/W4229881013","https://openalex.org/W2012014781","https://openalex.org/W1966262200","https://openalex.org/W2017736121","https://openalex.org/W1972395546","https://openalex.org/W2466591189"],"abstract_inverted_index":{"A":[0,93],"Field":[1],"Programmable":[2],"Gate":[3],"Array":[4],"(FPGA)":[5],"family":[6],"was":[7,101],"designed":[8,102],"to":[9,77],"match":[10],"a":[11,40,50],"programmable":[12,62],"fabric":[13,55,63],"die":[14,56],"built":[15],"in":[16],"14nm":[17],"process":[18],"technology":[19],"with":[20],"28Gb/s":[21],"transceiver":[22,41,59],"dice.":[23,60],"The":[24,61],"2.5D":[25],"packaging":[26],"(Fig.":[27],"3.3.1)":[28],"uses":[29],"embedded":[30,107],"interconnect":[31,73],"bridges":[32],"(EMIB)":[33],"[1].":[34],"20nm":[35],"transceivers":[36],"were":[37],"reused":[38],"enabling":[39],"roadmap":[42],"independent":[43],"of":[44,88],"FPGA":[45,90],"fabric.":[46],"Fig.":[47],"3.3.2":[48],"shows":[49],"560mm":[51],"<sup":[52],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[53],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">2</sup>":[54],"and":[57,71,86,103],"six":[58],"contains":[64],"2.8M":[65],"logic":[66],"elements,":[67],"DSP,":[68],"memory":[69],"components,":[70],"routing":[72],"operating":[74],"at":[75],"up":[76],"1GHz.":[78],"Applications":[79],"drove":[80],"the":[81,89],"need":[82],"for":[83],"improved":[84],"flexibility":[85],"security":[87],"configuration":[91],"system.":[92],"triple-modular":[94],"redundant":[95],"microprocessor-based":[96],"secure":[97],"device":[98],"manager":[99],"(SDM)":[100],"is":[104],"programmed":[105],"by":[106],"software.":[108]},"counts_by_year":[{"year":2025,"cited_by_count":3},{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":6},{"year":2022,"cited_by_count":3},{"year":2021,"cited_by_count":9},{"year":2020,"cited_by_count":12},{"year":2019,"cited_by_count":9},{"year":2018,"cited_by_count":9},{"year":2016,"cited_by_count":1}],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}
