{"id":"https://openalex.org/W2289464148","doi":"https://doi.org/10.1109/isscc.2016.7418045","title":"19.8 A 0.0021mm2 1.82mW 2.2GHz PLL using time-based integral control in 65nm CMOS","display_name":"19.8 A 0.0021mm2 1.82mW 2.2GHz PLL using time-based integral control in 65nm CMOS","publication_year":2016,"publication_date":"2016-01-01","ids":{"openalex":"https://openalex.org/W2289464148","doi":"https://doi.org/10.1109/isscc.2016.7418045","mag":"2289464148"},"language":"en","primary_location":{"id":"doi:10.1109/isscc.2016.7418045","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isscc.2016.7418045","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE International Solid-State Circuits Conference (ISSCC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5037002997","display_name":"Junheng Zhu","orcid":"https://orcid.org/0000-0002-0329-1769"},"institutions":[{"id":"https://openalex.org/I157725225","display_name":"University of Illinois Urbana-Champaign","ror":"https://ror.org/047426m28","country_code":"US","type":"education","lineage":["https://openalex.org/I157725225"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Junheng Zhu","raw_affiliation_strings":["University of Illinois, Urbana-Champaign, IL"],"affiliations":[{"raw_affiliation_string":"University of Illinois, Urbana-Champaign, IL","institution_ids":["https://openalex.org/I157725225"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5014466863","display_name":"Romesh Kumar Nandwana","orcid":"https://orcid.org/0000-0003-0339-5792"},"institutions":[{"id":"https://openalex.org/I157725225","display_name":"University of Illinois Urbana-Champaign","ror":"https://ror.org/047426m28","country_code":"US","type":"education","lineage":["https://openalex.org/I157725225"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Romesh Kumar Nandwana","raw_affiliation_strings":["University of Illinois, Urbana-Champaign, IL"],"affiliations":[{"raw_affiliation_string":"University of Illinois, Urbana-Champaign, IL","institution_ids":["https://openalex.org/I157725225"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5056891395","display_name":"Guanghua Shu","orcid":"https://orcid.org/0000-0001-7972-8616"},"institutions":[{"id":"https://openalex.org/I157725225","display_name":"University of Illinois Urbana-Champaign","ror":"https://ror.org/047426m28","country_code":"US","type":"education","lineage":["https://openalex.org/I157725225"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Guanghua Shu","raw_affiliation_strings":["University of Illinois, Urbana-Champaign, IL"],"affiliations":[{"raw_affiliation_string":"University of Illinois, Urbana-Champaign, IL","institution_ids":["https://openalex.org/I157725225"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5045287571","display_name":"Ahmed Elkholy","orcid":"https://orcid.org/0000-0002-3252-8585"},"institutions":[{"id":"https://openalex.org/I157725225","display_name":"University of Illinois Urbana-Champaign","ror":"https://ror.org/047426m28","country_code":"US","type":"education","lineage":["https://openalex.org/I157725225"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ahmed Elkholy","raw_affiliation_strings":["University of Illinois, Urbana-Champaign, IL"],"affiliations":[{"raw_affiliation_string":"University of Illinois, Urbana-Champaign, IL","institution_ids":["https://openalex.org/I157725225"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101565431","display_name":"Seong\u2010Joong Kim","orcid":"https://orcid.org/0000-0001-9096-8362"},"institutions":[{"id":"https://openalex.org/I157725225","display_name":"University of Illinois Urbana-Champaign","ror":"https://ror.org/047426m28","country_code":"US","type":"education","lineage":["https://openalex.org/I157725225"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Seong-Joong Kim","raw_affiliation_strings":["University of Illinois, Urbana-Champaign, IL"],"affiliations":[{"raw_affiliation_string":"University of Illinois, Urbana-Champaign, IL","institution_ids":["https://openalex.org/I157725225"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5036789252","display_name":"Pavan Kumar Hanumolu","orcid":"https://orcid.org/0000-0002-6233-8934"},"institutions":[{"id":"https://openalex.org/I157725225","display_name":"University of Illinois Urbana-Champaign","ror":"https://ror.org/047426m28","country_code":"US","type":"education","lineage":["https://openalex.org/I157725225"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Pavan Kumar Hanumolu","raw_affiliation_strings":["University of Illinois, Urbana-Champaign, IL"],"affiliations":[{"raw_affiliation_string":"University of Illinois, Urbana-Champaign, IL","institution_ids":["https://openalex.org/I157725225"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5037002997"],"corresponding_institution_ids":["https://openalex.org/I157725225"],"apc_list":null,"apc_paid":null,"fwci":1.8376,"has_fulltext":false,"cited_by_count":14,"citation_normalized_percentile":{"value":0.86160885,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"338","last_page":"340"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11444","display_name":"Electromagnetic Compatibility and Noise Suppression","score":0.9955000281333923,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9925000071525574,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.8450242280960083},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6246370077133179},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5823574066162109},{"id":"https://openalex.org/keywords/pll-multibit","display_name":"PLL multibit","score":0.5810894966125488},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.579041063785553},{"id":"https://openalex.org/keywords/clock-generator","display_name":"Clock generator","score":0.5624074339866638},{"id":"https://openalex.org/keywords/capacitor","display_name":"Capacitor","score":0.5481359362602234},{"id":"https://openalex.org/keywords/phase-noise","display_name":"Phase noise","score":0.4769771993160248},{"id":"https://openalex.org/keywords/voltage-controlled-oscillator","display_name":"Voltage-controlled oscillator","score":0.4397473633289337},{"id":"https://openalex.org/keywords/ring-oscillator","display_name":"Ring oscillator","score":0.43345773220062256},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.4273570477962494},{"id":"https://openalex.org/keywords/bandwidth","display_name":"Bandwidth (computing)","score":0.4272989332675934},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.4114258289337158},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.3908783495426178},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.11518040299415588},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.0962950587272644},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.09060457348823547}],"concepts":[{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.8450242280960083},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6246370077133179},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5823574066162109},{"id":"https://openalex.org/C77881186","wikidata":"https://www.wikidata.org/wiki/Q7119642","display_name":"PLL multibit","level":4,"score":0.5810894966125488},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.579041063785553},{"id":"https://openalex.org/C2778023540","wikidata":"https://www.wikidata.org/wiki/Q2164847","display_name":"Clock generator","level":4,"score":0.5624074339866638},{"id":"https://openalex.org/C52192207","wikidata":"https://www.wikidata.org/wiki/Q5322","display_name":"Capacitor","level":3,"score":0.5481359362602234},{"id":"https://openalex.org/C89631360","wikidata":"https://www.wikidata.org/wiki/Q1428766","display_name":"Phase noise","level":2,"score":0.4769771993160248},{"id":"https://openalex.org/C5291336","wikidata":"https://www.wikidata.org/wiki/Q852341","display_name":"Voltage-controlled oscillator","level":3,"score":0.4397473633289337},{"id":"https://openalex.org/C104111718","wikidata":"https://www.wikidata.org/wiki/Q2153973","display_name":"Ring oscillator","level":3,"score":0.43345773220062256},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4273570477962494},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.4272989332675934},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.4114258289337158},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.3908783495426178},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.11518040299415588},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0962950587272644},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.09060457348823547}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isscc.2016.7418045","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isscc.2016.7418045","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE International Solid-State Circuits Conference (ISSCC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8399999737739563,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W2099740767","https://openalex.org/W2105386586","https://openalex.org/W2112008043","https://openalex.org/W2118616136","https://openalex.org/W6676844732"],"related_works":["https://openalex.org/W984417604","https://openalex.org/W1486070987","https://openalex.org/W2217043549","https://openalex.org/W1600405202","https://openalex.org/W2976219355","https://openalex.org/W2301158783","https://openalex.org/W2133120878","https://openalex.org/W1972664199","https://openalex.org/W2369672785","https://openalex.org/W2376956425"],"abstract_inverted_index":{"Phase-locked":[0],"loops":[1],"(PLLs)":[2],"are":[3],"de-facto":[4],"clock":[5,20,59],"generators":[6],"in":[7,83,101,164,210,248,328],"analog,":[8],"digital,":[9],"RF,":[10],"and":[11,42,53,93,113,271,301,306,326,347],"embedded":[12],"systems":[13],"to":[14,36,56,89,109,146,179,206,239,258,263],"generate":[15],"a":[16,22,51,68,98,105,118,127,181,211,232,252,289,310,319,324],"high":[17,320],"frequency":[18,24,62],"output":[19,262],"from":[21],"low":[23,208],"reference":[25],"clock.":[26],"Modern":[27],"systems-on-chip":[28],"(SoCs)":[29],"require":[30],"many":[31],"such":[32,58],"PLLs":[33,66,140,303],"that":[34,73,292],"cater":[35],"multi-core":[37],"processors,":[38],"memories,":[39],"IO":[40],"interfaces":[41],"power":[43,212,235],"management.":[44],"A":[45],"ring-oscillator-based":[46,249],"analog":[47,65,297],"charge-pump":[48],"PLL":[49,100,193,223,290,316],"offers":[50],"flexible":[52],"power-efficient":[54],"way":[55],"implement":[57],"multipliers.":[60],"However,":[61,153],"compensation":[63],"of":[64,121,133,274,278,284,296],"requires":[67,104,317],"large":[69,269],"loop":[70,159,172],"filter":[71],"capacitor":[72,107,119,129,150,325],"occupies":[74,130,268],"significant":[75],"area.":[76,336],"The":[77,314],"area":[78,132,270,276,305],"penalty":[79],"is":[80,245],"further":[81],"exacerbated":[82],"deep":[84],"sub-micron":[85],"CMOS":[86,103],"processes":[87],"due":[88],"increasing":[90],"oscillator":[91,266],"gain":[92],"gate":[94],"leakage.":[95],"For":[96,215],"example,":[97],"2GHz":[99],"65nm":[102],"90pF":[106,128],"(R=1k\u03a9)":[108],"achieve":[110,207],"10MHz":[111],"bandwidth":[112,200,224],"70\u00b0":[114],"phase":[115,228],"margin.":[116],"Assuming":[117],"density":[120],"1fF/\u03bcm":[122],"<sup":[123,135,331],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[124,136,332,341],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">2</sup>":[125,137,333],",":[126],"an":[131,143],"0.09mm":[134],".":[138],"Digital":[139],"(DPLLs)":[141],"offer":[142],"attractive":[144],"means":[145],"eliminate":[147],"the":[148,162,170,176,192,226,260,264,275,294],"loop-filter":[149],"[1,":[151,280],"2].":[152,281],"quantization":[154,219,299],"error":[155,220],"added":[156],"by":[157,221,308],"its":[158,241],"components":[160],"degrades":[161],"performance":[163],"multiple":[165],"ways.":[166],"First,":[167],"it":[168,196,204],"makes":[169,203],"DPLL":[171],"inherently":[173],"non-linear":[174],"causing":[175],"steady":[177],"state":[178],"be":[180,237],"bounded":[182],"limit":[183],"cycle,":[184],"which":[185,202],"manifests":[186],"as":[187],"deterministic":[188],"jitter":[189,209,344],"(DJ)":[190],"at":[191,345],"output.":[194],"Second,":[195],"introduces":[197],"conflicting":[198],"noise":[199,229,242],"requirements,":[201],"difficult":[205],"efficient":[213],"manner.":[214],"instance,":[216],"suppressing":[217],"TDC":[218],"reducing":[222],"increases":[225],"DCO":[227,234],"contribution.":[230,243],"As":[231],"result,":[233],"must":[236],"increased":[238],"lower":[240],"This":[244],"especially":[246],"problematic":[247],"DPLLs.":[250],"Finally,":[251],"high-resolution":[253],"digital-to-analog":[254],"converter":[255],"(DAC)":[256],"needed":[257],"interface":[259],"DLF":[261],"ring":[265],"typically":[267],"negates":[272],"some":[273],"benefits":[277],"DPLLs":[279],"In":[282],"view":[283],"these":[285],"drawbacks,":[286],"we":[287],"present":[288],"architecture":[291],"combines":[293],"advantages":[295],"(no":[298],"error)":[300],"digital":[302],"(small":[304],"scalability)":[307],"using":[309],"time-based":[311],"integral":[312],"path.":[313],"prototype":[315],"neither":[318],"resolution":[321],"DAC":[322],"nor":[323],"fits":[327],"40\u03bcm\u00d752\u03bcm":[329],"(0.0021mm":[330],")":[334],"active":[335],"It":[337],"achieves":[338],"3.8ps":[339],"<sub":[340],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">rms</sub>":[342],"integrated":[343],"2.2GHz":[346],"consumes":[348],"1.82mW":[349],"power.":[350]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":7},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}