{"id":"https://openalex.org/W2291959676","doi":"https://doi.org/10.1109/isscc.2016.7418041","title":"19.4 A 0.17-to-3.5mW 0.15-to-5GHz SoC PLL with 15dB built-in supply noise rejection and self-bandwidth control in 14nm CMOS","display_name":"19.4 A 0.17-to-3.5mW 0.15-to-5GHz SoC PLL with 15dB built-in supply noise rejection and self-bandwidth control in 14nm CMOS","publication_year":2016,"publication_date":"2016-01-01","ids":{"openalex":"https://openalex.org/W2291959676","doi":"https://doi.org/10.1109/isscc.2016.7418041","mag":"2291959676"},"language":"en","primary_location":{"id":"doi:10.1109/isscc.2016.7418041","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isscc.2016.7418041","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE International Solid-State Circuits Conference (ISSCC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5102873292","display_name":"Kuan-Yueh James Shen","orcid":"https://orcid.org/0000-0003-2796-2683"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Kuan-Yueh James Shen","raw_affiliation_strings":["Intel, Hillsboro, OR"],"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5019254487","display_name":"Syed Feruz Syed Farooq","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Syed Feruz Syed Farooq","raw_affiliation_strings":["Intel, Hillsboro, OR"],"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5018623391","display_name":"Y. Fan","orcid":"https://orcid.org/0000-0001-5914-2765"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Yongping Fan","raw_affiliation_strings":["Intel, Hillsboro, OR"],"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5042110041","display_name":"Khoa Nguyen","orcid":"https://orcid.org/0000-0002-7638-6654"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Khoa Minh Nguyen","raw_affiliation_strings":["Intel, Hillsboro, OR"],"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100341380","display_name":"Qi Wang","orcid":"https://orcid.org/0000-0003-2645-5807"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Qi Wang","raw_affiliation_strings":["Intel, Hillsboro, OR"],"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5087380109","display_name":"Amr Elshazly","orcid":"https://orcid.org/0000-0002-0628-9138"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Amr Elshazly","raw_affiliation_strings":["Intel, Hillsboro, OR"],"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5034919212","display_name":"Nasser Kurd","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Nasser Kurd","raw_affiliation_strings":["Intel, Hillsboro, OR"],"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":7,"corresponding_author_ids":["https://openalex.org/A5102873292"],"corresponding_institution_ids":["https://openalex.org/I1343180700"],"apc_list":null,"apc_paid":null,"fwci":2.603,"has_fulltext":false,"cited_by_count":42,"citation_normalized_percentile":{"value":0.9012124,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":90,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"330","last_page":"331"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10299","display_name":"Photonic and Optical Devices","score":0.9944999814033508,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11429","display_name":"Semiconductor Lasers and Optical Devices","score":0.9916999936103821,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.8941690921783447},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.6512064933776855},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6002849340438843},{"id":"https://openalex.org/keywords/pll-multibit","display_name":"PLL multibit","score":0.5851162075996399},{"id":"https://openalex.org/keywords/bandwidth","display_name":"Bandwidth (computing)","score":0.5612605810165405},{"id":"https://openalex.org/keywords/phase-noise","display_name":"Phase noise","score":0.5553914308547974},{"id":"https://openalex.org/keywords/modular-design","display_name":"Modular design","score":0.5343286991119385},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5041273832321167},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.41387176513671875},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.34381598234176636},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3399532437324524},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.16730371117591858}],"concepts":[{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.8941690921783447},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.6512064933776855},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6002849340438843},{"id":"https://openalex.org/C77881186","wikidata":"https://www.wikidata.org/wiki/Q7119642","display_name":"PLL multibit","level":4,"score":0.5851162075996399},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.5612605810165405},{"id":"https://openalex.org/C89631360","wikidata":"https://www.wikidata.org/wiki/Q1428766","display_name":"Phase noise","level":2,"score":0.5553914308547974},{"id":"https://openalex.org/C101468663","wikidata":"https://www.wikidata.org/wiki/Q1620158","display_name":"Modular design","level":2,"score":0.5343286991119385},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5041273832321167},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.41387176513671875},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.34381598234176636},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3399532437324524},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.16730371117591858},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isscc.2016.7418041","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isscc.2016.7418041","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE International Solid-State Circuits Conference (ISSCC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W1953939323","https://openalex.org/W1966797259","https://openalex.org/W1971575710","https://openalex.org/W2022512492","https://openalex.org/W2038284388","https://openalex.org/W2069385386","https://openalex.org/W2075004943","https://openalex.org/W2118616136","https://openalex.org/W3152162041","https://openalex.org/W6641045975","https://openalex.org/W6643191815"],"related_works":["https://openalex.org/W1576949837","https://openalex.org/W984417604","https://openalex.org/W2104055211","https://openalex.org/W2474043983","https://openalex.org/W2544336511","https://openalex.org/W2566880546","https://openalex.org/W2078513307","https://openalex.org/W1978186604","https://openalex.org/W2144737022","https://openalex.org/W2124954209"],"abstract_inverted_index":{"With":[0],"recent":[1],"advancements":[2],"in":[3],"SoC":[4,7,18],"integration,":[5],"modern":[6],"architectures":[8],"can":[9],"employ":[10],"more":[11],"than":[12],"20":[13],"PLLs":[14],"[1].":[15],"To":[16],"address":[17],"clocking":[19],"needs":[20],"with":[21],"an":[22],"ever":[23],"reducing":[24],"power":[25],"budget,":[26],"a":[27,34,49,66,77,83],"deep":[28],"sub-mW":[29],"to":[30,42,74],"low-mW":[31],"PLL":[32,47],"having":[33],"FoM":[35],"between":[36],"-226dB":[37],"and":[38,52,87],"-234dB":[39],"from":[40,76],"0.8GHz":[41],"5GHz":[43],"is":[44],"presented.":[45],"The":[46,69],"features":[48],"modular":[50],"implementation":[51],"therefore":[53],"could":[54],"be":[55],"used":[56],"as":[57,63],"the":[58],"local":[59],"clock":[60],"source":[61],"or":[62],"part":[64],"of":[65,85],"clock-generation":[67],"hub.":[68],"hub":[70],"provides":[71],"reference":[72],"clocks":[73],"subsystems":[75],"single":[78],"platform":[79],"crystal":[80],"oscillator":[81],"through":[82],"combination":[84],"divisions":[86],"distributions.":[88]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":4},{"year":2024,"cited_by_count":4},{"year":2023,"cited_by_count":3},{"year":2022,"cited_by_count":3},{"year":2021,"cited_by_count":8},{"year":2020,"cited_by_count":5},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":6},{"year":2017,"cited_by_count":5},{"year":2016,"cited_by_count":2}],"updated_date":"2026-04-18T07:56:08.524223","created_date":"2025-10-10T00:00:00"}
