{"id":"https://openalex.org/W2290824897","doi":"https://doi.org/10.1109/isscc.2016.7417942","title":"7.2 4Mb STT-MRAM-based cache with memory-access-aware power optimization and write-verify-write / read-modify-write scheme","display_name":"7.2 4Mb STT-MRAM-based cache with memory-access-aware power optimization and write-verify-write / read-modify-write scheme","publication_year":2016,"publication_date":"2016-01-01","ids":{"openalex":"https://openalex.org/W2290824897","doi":"https://doi.org/10.1109/isscc.2016.7417942","mag":"2290824897"},"language":"en","primary_location":{"id":"doi:10.1109/isscc.2016.7417942","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isscc.2016.7417942","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE International Solid-State Circuits Conference (ISSCC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5103020387","display_name":"Hiroki Noguchi","orcid":"https://orcid.org/0000-0003-1659-1389"},"institutions":[{"id":"https://openalex.org/I1292669757","display_name":"Toshiba (Japan)","ror":"https://ror.org/0326v3z14","country_code":"JP","type":"company","lineage":["https://openalex.org/I1292669757"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"Hiroki Noguchi","raw_affiliation_strings":["Toshiba, Kawasaki, Japan"],"affiliations":[{"raw_affiliation_string":"Toshiba, Kawasaki, Japan","institution_ids":["https://openalex.org/I1292669757"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5034034258","display_name":"Kazutaka Ikegami","orcid":"https://orcid.org/0000-0002-6234-4568"},"institutions":[{"id":"https://openalex.org/I1292669757","display_name":"Toshiba (Japan)","ror":"https://ror.org/0326v3z14","country_code":"JP","type":"company","lineage":["https://openalex.org/I1292669757"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Kazutaka Ikegami","raw_affiliation_strings":["Toshiba, Kawasaki, Japan"],"affiliations":[{"raw_affiliation_string":"Toshiba, Kawasaki, Japan","institution_ids":["https://openalex.org/I1292669757"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111938114","display_name":"Satoshi Takaya","orcid":"https://orcid.org/0000-0001-9402-1694"},"institutions":[{"id":"https://openalex.org/I1292669757","display_name":"Toshiba (Japan)","ror":"https://ror.org/0326v3z14","country_code":"JP","type":"company","lineage":["https://openalex.org/I1292669757"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Satoshi Takaya","raw_affiliation_strings":["Toshiba, Kawasaki, Japan"],"affiliations":[{"raw_affiliation_string":"Toshiba, Kawasaki, Japan","institution_ids":["https://openalex.org/I1292669757"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5087319091","display_name":"Eishi Arima","orcid":"https://orcid.org/0009-0002-7043-4288"},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Eishi Arima","raw_affiliation_strings":["Tokyo Daigaku, Bunkyo-ku, Tokyo, JP"],"affiliations":[{"raw_affiliation_string":"Tokyo Daigaku, Bunkyo-ku, Tokyo, JP","institution_ids":["https://openalex.org/I74801974"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5044735538","display_name":"K. Kushida","orcid":null},"institutions":[{"id":"https://openalex.org/I1292669757","display_name":"Toshiba (Japan)","ror":"https://ror.org/0326v3z14","country_code":"JP","type":"company","lineage":["https://openalex.org/I1292669757"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Keiichi Kushida","raw_affiliation_strings":["Toshiba, Kawasaki, Japan"],"affiliations":[{"raw_affiliation_string":"Toshiba, Kawasaki, Japan","institution_ids":["https://openalex.org/I1292669757"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5080211932","display_name":"Atsushi Kawasumi","orcid":null},"institutions":[{"id":"https://openalex.org/I1292669757","display_name":"Toshiba (Japan)","ror":"https://ror.org/0326v3z14","country_code":"JP","type":"company","lineage":["https://openalex.org/I1292669757"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Atsushi Kawasumi","raw_affiliation_strings":["Toshiba, Kawasaki, Japan"],"affiliations":[{"raw_affiliation_string":"Toshiba, Kawasaki, Japan","institution_ids":["https://openalex.org/I1292669757"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5105675534","display_name":"Hiroyuki Hara","orcid":null},"institutions":[{"id":"https://openalex.org/I1292669757","display_name":"Toshiba (Japan)","ror":"https://ror.org/0326v3z14","country_code":"JP","type":"company","lineage":["https://openalex.org/I1292669757"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Hiroyuki Hara","raw_affiliation_strings":["Toshiba, Kawasaki, Japan"],"affiliations":[{"raw_affiliation_string":"Toshiba, Kawasaki, Japan","institution_ids":["https://openalex.org/I1292669757"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5004388848","display_name":"Keiko Abe","orcid":"https://orcid.org/0000-0001-5844-8199"},"institutions":[{"id":"https://openalex.org/I1292669757","display_name":"Toshiba (Japan)","ror":"https://ror.org/0326v3z14","country_code":"JP","type":"company","lineage":["https://openalex.org/I1292669757"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Keiko Abe","raw_affiliation_strings":["Toshiba, Kawasaki, Japan"],"affiliations":[{"raw_affiliation_string":"Toshiba, Kawasaki, Japan","institution_ids":["https://openalex.org/I1292669757"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5109190190","display_name":"Naoharu Shimomura","orcid":null},"institutions":[{"id":"https://openalex.org/I1292669757","display_name":"Toshiba (Japan)","ror":"https://ror.org/0326v3z14","country_code":"JP","type":"company","lineage":["https://openalex.org/I1292669757"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Naoharu Shimomura","raw_affiliation_strings":["Toshiba, Kawasaki, Japan"],"affiliations":[{"raw_affiliation_string":"Toshiba, Kawasaki, Japan","institution_ids":["https://openalex.org/I1292669757"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5031270865","display_name":"Junichi Ito","orcid":null},"institutions":[{"id":"https://openalex.org/I1292669757","display_name":"Toshiba (Japan)","ror":"https://ror.org/0326v3z14","country_code":"JP","type":"company","lineage":["https://openalex.org/I1292669757"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Junichi Ito","raw_affiliation_strings":["Toshiba, Kawasaki, Japan"],"affiliations":[{"raw_affiliation_string":"Toshiba, Kawasaki, Japan","institution_ids":["https://openalex.org/I1292669757"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111734510","display_name":"Shinobu Fujita","orcid":null},"institutions":[{"id":"https://openalex.org/I1292669757","display_name":"Toshiba (Japan)","ror":"https://ror.org/0326v3z14","country_code":"JP","type":"company","lineage":["https://openalex.org/I1292669757"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Shinobu Fujita","raw_affiliation_strings":["Toshiba, Kawasaki, Japan"],"affiliations":[{"raw_affiliation_string":"Toshiba, Kawasaki, Japan","institution_ids":["https://openalex.org/I1292669757"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5042516424","display_name":"Takashi Nakada","orcid":"https://orcid.org/0000-0001-7512-2545"},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Takashi Nakada","raw_affiliation_strings":["University of Tokyo, Tokyo, Japan"],"affiliations":[{"raw_affiliation_string":"University of Tokyo, Tokyo, Japan","institution_ids":["https://openalex.org/I74801974"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5090578339","display_name":"Hiroshi Nakamura","orcid":"https://orcid.org/0009-0005-6505-1903"},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Hiroshi Nakamura","raw_affiliation_strings":["University of Tokyo, Tokyo, Japan"],"affiliations":[{"raw_affiliation_string":"University of Tokyo, Tokyo, Japan","institution_ids":["https://openalex.org/I74801974"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":13,"corresponding_author_ids":["https://openalex.org/A5103020387"],"corresponding_institution_ids":["https://openalex.org/I1292669757"],"apc_list":null,"apc_paid":null,"fwci":4.9616,"has_fulltext":false,"cited_by_count":68,"citation_normalized_percentile":{"value":0.95508151,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":96,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"132","last_page":"133"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10049","display_name":"Magnetic properties of thin films","score":0.9976999759674072,"subfield":{"id":"https://openalex.org/subfields/3107","display_name":"Atomic and Molecular Physics, and Optics"},"field":{"id":"https://openalex.org/fields/31","display_name":"Physics and Astronomy"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7922800779342651},{"id":"https://openalex.org/keywords/magnetoresistive-random-access-memory","display_name":"Magnetoresistive random-access memory","score":0.7489520311355591},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.5810003876686096},{"id":"https://openalex.org/keywords/page-cache","display_name":"Page cache","score":0.4638056755065918},{"id":"https://openalex.org/keywords/non-volatile-memory","display_name":"Non-volatile memory","score":0.4634734094142914},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.45583274960517883},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.42111632227897644},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4172464609146118},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.4139612913131714},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.4115397036075592},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.38014641404151917},{"id":"https://openalex.org/keywords/cache-algorithms","display_name":"Cache algorithms","score":0.22207096219062805},{"id":"https://openalex.org/keywords/random-access-memory","display_name":"Random access memory","score":0.09561792016029358}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7922800779342651},{"id":"https://openalex.org/C46891859","wikidata":"https://www.wikidata.org/wiki/Q1061546","display_name":"Magnetoresistive random-access memory","level":3,"score":0.7489520311355591},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.5810003876686096},{"id":"https://openalex.org/C36340418","wikidata":"https://www.wikidata.org/wiki/Q7124288","display_name":"Page cache","level":5,"score":0.4638056755065918},{"id":"https://openalex.org/C177950962","wikidata":"https://www.wikidata.org/wiki/Q10997658","display_name":"Non-volatile memory","level":2,"score":0.4634734094142914},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.45583274960517883},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.42111632227897644},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4172464609146118},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.4139612913131714},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.4115397036075592},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.38014641404151917},{"id":"https://openalex.org/C38556500","wikidata":"https://www.wikidata.org/wiki/Q13404475","display_name":"Cache algorithms","level":4,"score":0.22207096219062805},{"id":"https://openalex.org/C2994168587","wikidata":"https://www.wikidata.org/wiki/Q5295","display_name":"Random access memory","level":2,"score":0.09561792016029358}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isscc.2016.7417942","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isscc.2016.7417942","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE International Solid-State Circuits Conference (ISSCC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.8999999761581421,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W1966058111","https://openalex.org/W2075278406","https://openalex.org/W2100088734","https://openalex.org/W2201475267","https://openalex.org/W6675050829"],"related_works":["https://openalex.org/W2342993049","https://openalex.org/W2171162600","https://openalex.org/W2601736132","https://openalex.org/W2700018028","https://openalex.org/W2505369450","https://openalex.org/W2315140189","https://openalex.org/W248835169","https://openalex.org/W4234756210","https://openalex.org/W1977963439","https://openalex.org/W1993178305"],"abstract_inverted_index":{"Two":[0],"performance":[1],"gaps":[2],"in":[3],"the":[4,65,91,189],"memory":[5,15,33,51,60,155,159,179],"hierarchy,":[6],"between":[7],"CPU":[8],"cache":[9,85,146,154,163,178,183],"and":[10,13,16,73,100,117,162,177],"main":[11,14],"memory,":[12],"mass":[17],"storage,":[18],"will":[19],"become":[20],"increasingly":[21],"severe":[22],"bottlenecks":[23],"for":[24,52,145],"computing-system":[25],"performance.":[26],"Although":[27],"it":[28],"is":[29,61,87,199],"necessary":[30],"to":[31,35,63,89,143,187,201],"increase":[32],"capacity":[34],"fill":[36,64,90],"these":[37],"gaps,":[38],"power":[39,168,172,204],"also":[40],"increases":[41],"when":[42],"conventional":[43],"volatile":[44],"memories":[45],"are":[46],"used.":[47],"A":[48],"new":[49],"nonvolatile":[50,82],"this":[53],"purpose":[54],"has":[55,96,123,184],"been":[56,115],"anticipated.":[57],"Storage":[58],"class":[59],"used":[62,88],"second":[66],"gap.":[67,93],"Many":[68],"candidates":[69],"exist:":[70],"ReRAM,":[71],"PRAM,":[72],"3D-cross":[74],"point":[75],"type":[76],"with":[77,103,120,170,192],"resistive":[78],"change":[79],"RAM.":[80],"However,":[81],"last":[83,152],"level":[84,153],"(LLC)":[86,156],"first":[92],"Advanced":[94],"STT-MRAM":[95,119,133,216],"achieved":[97],"sub-4ns":[98],"read":[99],"write":[101],"accesses":[102],"perpendicular":[104],"magnetic":[105],"tunnel":[106],"junctions":[107],"(p-MTJ)":[108],"[1-2].":[109],"Furthermore,":[110,195],"mature":[111],"integration":[112],"processes":[113],"have":[114],"developed":[116],"8Mb":[118],"sub-5ns":[121],"operation":[122,136],"shown":[124],"high":[125,185],"reliability":[126,186],"[3].":[127],"Moreover,":[128],"because":[129],"of":[130,213],"its":[131],"non-volatility,":[132],"can":[134],"reduce":[135,188,202],"energy":[137],"by":[138],"more":[139],"than":[140],"81%":[141],"compared":[142],"SRAM":[144],"[1].":[147],"This":[148],"paper":[149],"presents":[150,209],"STT-MRAM-based":[151,182],"including":[157],"MRAM":[158],"core,":[160],"peripherals":[161],"logic":[164],"circuits,":[165],"using":[166],"novel":[167,193],"optimization":[169],"high-speed":[171],"gating":[173],"(HS-PG),considering":[174],"processor":[175],"architectures":[176],"accesses.":[180],"The":[181],"write-error":[190],"rate":[191],"write-verify-write.":[194],"a":[196,210,214],"read-modify-write":[197],"scheme":[198],"implemented":[200],"active":[203],"without":[205],"penalty.":[206],"Figure":[207],"7.2.1":[208],"block":[211],"diagram":[212],"4Mb":[215],"based":[217],"cache.":[218]},"counts_by_year":[{"year":2025,"cited_by_count":3},{"year":2024,"cited_by_count":4},{"year":2023,"cited_by_count":5},{"year":2022,"cited_by_count":8},{"year":2021,"cited_by_count":8},{"year":2020,"cited_by_count":13},{"year":2019,"cited_by_count":10},{"year":2018,"cited_by_count":7},{"year":2017,"cited_by_count":6},{"year":2016,"cited_by_count":4}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}