{"id":"https://openalex.org/W2087345965","doi":"https://doi.org/10.1109/isscc.2015.7063050","title":"17.1 A 0.6V 1.5GHz 84Mb SRAM design in 14nm FinFET CMOS technology","display_name":"17.1 A 0.6V 1.5GHz 84Mb SRAM design in 14nm FinFET CMOS technology","publication_year":2015,"publication_date":"2015-02-01","ids":{"openalex":"https://openalex.org/W2087345965","doi":"https://doi.org/10.1109/isscc.2015.7063050","mag":"2087345965"},"language":"en","primary_location":{"id":"doi:10.1109/isscc.2015.7063050","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isscc.2015.7063050","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5053857493","display_name":"Eric Karl","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Eric Karl","raw_affiliation_strings":["Intel, Hillsboro, OR","Intel, Hillsboro OR"],"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel, Hillsboro OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5007891380","display_name":"Zheng Guo","orcid":"https://orcid.org/0000-0001-8615-9749"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Zheng Guo","raw_affiliation_strings":["Intel, Hillsboro, OR","Intel, Hillsboro OR"],"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel, Hillsboro OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5072797522","display_name":"James W. Conary","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"James W. Conary","raw_affiliation_strings":["Intel, Hillsboro, OR","Intel, Hillsboro OR"],"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel, Hillsboro OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103483122","display_name":"Jeffrey L. Miller","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jeffrey L. Miller","raw_affiliation_strings":["Intel, Hillsboro, OR","Intel, Hillsboro OR"],"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel, Hillsboro OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5036589180","display_name":"Yong-Gee Ng","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Yong-Gee Ng","raw_affiliation_strings":["Intel, Hillsboro, OR","Intel, Hillsboro OR"],"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel, Hillsboro OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5050071437","display_name":"Satyanand Nalam","orcid":"https://orcid.org/0000-0002-6767-1752"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Satyanand Nalam","raw_affiliation_strings":["Intel, Hillsboro, OR","Intel, Hillsboro OR"],"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel, Hillsboro OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100644921","display_name":"Daeyeon Kim","orcid":"https://orcid.org/0000-0002-5879-8313"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Daeyeon Kim","raw_affiliation_strings":["Intel, Hillsboro, OR","Intel, Hillsboro OR"],"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel, Hillsboro OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102812519","display_name":"John Keane","orcid":"https://orcid.org/0000-0002-9746-8990"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"John Keane","raw_affiliation_strings":["Intel, Hillsboro, OR","Intel, Hillsboro OR"],"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel, Hillsboro OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103485789","display_name":"Uddalak Bhattacharya","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Uddalak Bhattacharya","raw_affiliation_strings":["Intel, Hillsboro, OR","Intel, Hillsboro OR"],"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel, Hillsboro OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":null,"display_name":"Kevin Zhang","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Kevin Zhang","raw_affiliation_strings":["Intel, Hillsboro, OR","Intel, Hillsboro OR"],"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel, Hillsboro OR","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":10,"corresponding_author_ids":["https://openalex.org/A5053857493"],"corresponding_institution_ids":["https://openalex.org/I1343180700"],"apc_list":null,"apc_paid":null,"fwci":5.8211,"has_fulltext":false,"cited_by_count":45,"citation_normalized_percentile":{"value":0.96444362,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":100},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"3"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.7327989339828491},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.631017804145813},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.5206558108329773},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.48418477177619934},{"id":"https://openalex.org/keywords/node","display_name":"Node (physics)","score":0.48109716176986694},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.4531921446323395},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.4482635259628296},{"id":"https://openalex.org/keywords/subthreshold-conduction","display_name":"Subthreshold conduction","score":0.44490885734558105},{"id":"https://openalex.org/keywords/quantization","display_name":"Quantization (signal processing)","score":0.44314876198768616},{"id":"https://openalex.org/keywords/threshold-voltage","display_name":"Threshold voltage","score":0.4270550608634949},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.41344916820526123},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.37912851572036743},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.23928841948509216},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.06844067573547363}],"concepts":[{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.7327989339828491},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.631017804145813},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.5206558108329773},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.48418477177619934},{"id":"https://openalex.org/C62611344","wikidata":"https://www.wikidata.org/wiki/Q1062658","display_name":"Node (physics)","level":2,"score":0.48109716176986694},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4531921446323395},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.4482635259628296},{"id":"https://openalex.org/C156465305","wikidata":"https://www.wikidata.org/wiki/Q1658601","display_name":"Subthreshold conduction","level":4,"score":0.44490885734558105},{"id":"https://openalex.org/C28855332","wikidata":"https://www.wikidata.org/wiki/Q198099","display_name":"Quantization (signal processing)","level":2,"score":0.44314876198768616},{"id":"https://openalex.org/C195370968","wikidata":"https://www.wikidata.org/wiki/Q1754002","display_name":"Threshold voltage","level":4,"score":0.4270550608634949},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.41344916820526123},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.37912851572036743},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.23928841948509216},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.06844067573547363},{"id":"https://openalex.org/C66938386","wikidata":"https://www.wikidata.org/wiki/Q633538","display_name":"Structural engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isscc.2015.7063050","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isscc.2015.7063050","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.8799999952316284}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W1965287694","https://openalex.org/W1966797259","https://openalex.org/W1998798369","https://openalex.org/W2073818373","https://openalex.org/W2096288219"],"related_works":["https://openalex.org/W2806295079","https://openalex.org/W2117824263","https://openalex.org/W2134421493","https://openalex.org/W2489257435","https://openalex.org/W2009852498","https://openalex.org/W1991521745","https://openalex.org/W3004587385","https://openalex.org/W4220771873","https://openalex.org/W2786811717","https://openalex.org/W2109147260"],"abstract_inverted_index":{"The":[0,89],"growth":[1],"of":[2,12,43,58,66,91,179],"battery-powered":[3],"mobile":[4],"and":[5,15,78,104,136,177],"wearable":[6],"devices":[7,93],"has":[8],"increased":[9,86],"the":[10,24,49,64,95,155],"importance":[11],"low-power":[13,189],"operation":[14,191,207],"cost":[16],"in":[17,116,147,184,208],"system-on-a-chip":[18],"(SoC)":[19],"design.":[20],"Supply-voltage":[21],"scaling":[22,36],"is":[23,182],"predominant":[25],"approach":[26],"to":[27,63,85,108,132,139,186],"active":[28],"power":[29,87],"reduction":[30,115,146],"for":[31,37,70,165],"SoC":[32],"design,":[33,60],"including":[34],"voltage":[35,52,68,83,118],"on-die":[38,71],"memory":[39,44,80,190],"given":[40],"increasing":[41],"levels":[42],"integration.":[45],"SRAM":[46,148,168,202],"can":[47],"limit":[48],"minimum":[50],"operating":[51,79],"(V":[53],"<inf":[54,127,150],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[55,128,151,216],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">MIN</inf>":[56,152],")":[57],"a":[59,120,144,163,209],"often":[61],"leading":[62],"introduction":[65,90],"separate":[67],"supplies":[69,74],"memory.":[72],"Additional":[73],"increase":[75],"platform":[76],"cost,":[77],"at":[81,94,192],"higher":[82],"leads":[84],"consumption.":[88],"trigate":[92],"22nm":[96],"technology":[97,113,157,176,212],"node":[98],"delivered":[99],"superior":[100],"short":[101],"channel":[102],"effects":[103],"subthreshold":[105],"slope":[106],"relative":[107],"existing":[109],"bulk":[110],"planar":[111],"device":[112,134],"enabling":[114],"threshold":[117],"within":[119],"fixed":[121],"leakage":[122],"constraint.":[123],"Lower":[124],"transistor":[125],"V":[126,149],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">th</inf>":[129],",":[130],"improvements":[131],"random":[133],"variability,":[135],"assist":[137],"circuits":[138,181],"overcome":[140],"device-size":[141,160],"quantization":[142,161],"enabled":[143],">150mV":[145],"[1].":[153],"At":[154],"14nm":[156,210],"node,":[158],"FinFET":[159,219],"remains":[162],"challenge":[164],"compact":[166],"6T":[167],"bitcells":[169],"with":[170,205],"minimum-size":[171],"transistors.":[172,220],"Careful":[173],"co-optimization":[174],"between":[175],"design":[178,204],"memory-assist":[180],"required":[183],"order":[185],"deliver":[187],"dense,":[188],"low":[193],"voltages.":[194],"In":[195],"this":[196],"paper,":[197],"we":[198],"present":[199],"an":[200],"84Mb":[201],"array":[203],"wide-voltage-range":[206],"logic":[211],"featuring":[213],"2":[214],"<sup":[215],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">nd</sup>":[217],"-generation":[218]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2024,"cited_by_count":2},{"year":2023,"cited_by_count":2},{"year":2022,"cited_by_count":3},{"year":2021,"cited_by_count":3},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":3},{"year":2018,"cited_by_count":6},{"year":2017,"cited_by_count":4},{"year":2016,"cited_by_count":17},{"year":2015,"cited_by_count":2}],"updated_date":"2026-04-21T08:09:41.155169","created_date":"2025-10-10T00:00:00"}