{"id":"https://openalex.org/W2019720625","doi":"https://doi.org/10.1109/isscc.2015.7063021","title":"14.1 A 0.048mm<sup>2</sup> 3mW synthesizable fractional-N PLL with a soft injection-locking technique","display_name":"14.1 A 0.048mm<sup>2</sup> 3mW synthesizable fractional-N PLL with a soft injection-locking technique","publication_year":2015,"publication_date":"2015-02-01","ids":{"openalex":"https://openalex.org/W2019720625","doi":"https://doi.org/10.1109/isscc.2015.7063021","mag":"2019720625"},"language":"en","primary_location":{"id":"doi:10.1109/isscc.2015.7063021","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isscc.2015.7063021","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5074494245","display_name":"Wei Deng","orcid":"https://orcid.org/0000-0002-6323-4539"},"institutions":[{"id":"https://openalex.org/I114531698","display_name":"Tokyo Institute of Technology","ror":"https://ror.org/0112mx960","country_code":"JP","type":"education","lineage":["https://openalex.org/I114531698"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Wei Deng","raw_affiliation_strings":["Tokyo Institute of Technology, Tokyo, Japan","[Tokyo Institute of Technology, Tokyo, JAPAN]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Tokyo Institute of Technology, Tokyo, Japan","institution_ids":["https://openalex.org/I114531698"]},{"raw_affiliation_string":"[Tokyo Institute of Technology, Tokyo, JAPAN]","institution_ids":["https://openalex.org/I114531698"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5040405791","display_name":"Dongsheng Yang","orcid":"https://orcid.org/0000-0002-1808-1908"},"institutions":[{"id":"https://openalex.org/I114531698","display_name":"Tokyo Institute of Technology","ror":"https://ror.org/0112mx960","country_code":"JP","type":"education","lineage":["https://openalex.org/I114531698"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Dongsheng Yang","raw_affiliation_strings":["Tokyo Institute of Technology, Tokyo, Japan","[Tokyo Institute of Technology, Tokyo, JAPAN]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Tokyo Institute of Technology, Tokyo, Japan","institution_ids":["https://openalex.org/I114531698"]},{"raw_affiliation_string":"[Tokyo Institute of Technology, Tokyo, JAPAN]","institution_ids":["https://openalex.org/I114531698"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5032076900","display_name":"Aravind Tharayil Narayanan","orcid":"https://orcid.org/0000-0002-6053-6603"},"institutions":[{"id":"https://openalex.org/I114531698","display_name":"Tokyo Institute of Technology","ror":"https://ror.org/0112mx960","country_code":"JP","type":"education","lineage":["https://openalex.org/I114531698"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Aravind Tharayil Narayanan","raw_affiliation_strings":["Tokyo Institute of Technology, Tokyo, Japan","[Tokyo Institute of Technology, Tokyo, JAPAN]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Tokyo Institute of Technology, Tokyo, Japan","institution_ids":["https://openalex.org/I114531698"]},{"raw_affiliation_string":"[Tokyo Institute of Technology, Tokyo, JAPAN]","institution_ids":["https://openalex.org/I114531698"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5110431996","display_name":"Kengo Nakata","orcid":null},"institutions":[{"id":"https://openalex.org/I114531698","display_name":"Tokyo Institute of Technology","ror":"https://ror.org/0112mx960","country_code":"JP","type":"education","lineage":["https://openalex.org/I114531698"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Kengo Nakata","raw_affiliation_strings":["Tokyo Institute of Technology, Tokyo, Japan","[Tokyo Institute of Technology, Tokyo, JAPAN]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Tokyo Institute of Technology, Tokyo, Japan","institution_ids":["https://openalex.org/I114531698"]},{"raw_affiliation_string":"[Tokyo Institute of Technology, Tokyo, JAPAN]","institution_ids":["https://openalex.org/I114531698"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5050565374","display_name":"Teerachot Siriburanon","orcid":"https://orcid.org/0000-0003-1658-9596"},"institutions":[{"id":"https://openalex.org/I114531698","display_name":"Tokyo Institute of Technology","ror":"https://ror.org/0112mx960","country_code":"JP","type":"education","lineage":["https://openalex.org/I114531698"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Teerachot Siriburanon","raw_affiliation_strings":["Tokyo Kogyo Daigaku, Meguro-ku, Tokyo, JP","[Tokyo Institute of Technology, Tokyo, JAPAN]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Tokyo Kogyo Daigaku, Meguro-ku, Tokyo, JP","institution_ids":["https://openalex.org/I114531698"]},{"raw_affiliation_string":"[Tokyo Institute of Technology, Tokyo, JAPAN]","institution_ids":["https://openalex.org/I114531698"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5064086312","display_name":"Kenichi Okada","orcid":"https://orcid.org/0000-0002-1082-7672"},"institutions":[{"id":"https://openalex.org/I114531698","display_name":"Tokyo Institute of Technology","ror":"https://ror.org/0112mx960","country_code":"JP","type":"education","lineage":["https://openalex.org/I114531698"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Kenichi Okada","raw_affiliation_strings":["Tokyo Institute of Technology, Tokyo, Japan","[Tokyo Institute of Technology, Tokyo, JAPAN]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Tokyo Institute of Technology, Tokyo, Japan","institution_ids":["https://openalex.org/I114531698"]},{"raw_affiliation_string":"[Tokyo Institute of Technology, Tokyo, JAPAN]","institution_ids":["https://openalex.org/I114531698"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5111453629","display_name":"Akira Matsuzawa","orcid":null},"institutions":[{"id":"https://openalex.org/I114531698","display_name":"Tokyo Institute of Technology","ror":"https://ror.org/0112mx960","country_code":"JP","type":"education","lineage":["https://openalex.org/I114531698"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Akira Matsuzawa","raw_affiliation_strings":["Tokyo Institute of Technology, Tokyo, Japan","[Tokyo Institute of Technology, Tokyo, JAPAN]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Tokyo Institute of Technology, Tokyo, Japan","institution_ids":["https://openalex.org/I114531698"]},{"raw_affiliation_string":"[Tokyo Institute of Technology, Tokyo, JAPAN]","institution_ids":["https://openalex.org/I114531698"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I114531698"],"apc_list":null,"apc_paid":null,"fwci":9.0587,"has_fulltext":false,"cited_by_count":49,"citation_normalized_percentile":{"value":0.98970261,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":93,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"3"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11429","display_name":"Semiconductor Lasers and Optical Devices","score":0.98089998960495,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11444","display_name":"Electromagnetic Compatibility and Noise Suppression","score":0.98089998960495,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.7824758291244507},{"id":"https://openalex.org/keywords/phase-noise","display_name":"Phase noise","score":0.6720637679100037},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5928827524185181},{"id":"https://openalex.org/keywords/ring-oscillator","display_name":"Ring oscillator","score":0.5751903057098389},{"id":"https://openalex.org/keywords/pll-multibit","display_name":"PLL multibit","score":0.5123113393783569},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5012931823730469},{"id":"https://openalex.org/keywords/time-to-digital-converter","display_name":"Time-to-digital converter","score":0.43181464076042175},{"id":"https://openalex.org/keywords/bandwidth","display_name":"Bandwidth (computing)","score":0.4312761127948761},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.35048478841781616},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.339627206325531},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.23086422681808472},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.1920395791530609},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.17622220516204834},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.12772083282470703},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.11548653244972229}],"concepts":[{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.7824758291244507},{"id":"https://openalex.org/C89631360","wikidata":"https://www.wikidata.org/wiki/Q1428766","display_name":"Phase noise","level":2,"score":0.6720637679100037},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5928827524185181},{"id":"https://openalex.org/C104111718","wikidata":"https://www.wikidata.org/wiki/Q2153973","display_name":"Ring oscillator","level":3,"score":0.5751903057098389},{"id":"https://openalex.org/C77881186","wikidata":"https://www.wikidata.org/wiki/Q7119642","display_name":"PLL multibit","level":4,"score":0.5123113393783569},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5012931823730469},{"id":"https://openalex.org/C99594498","wikidata":"https://www.wikidata.org/wiki/Q2434524","display_name":"Time-to-digital converter","level":4,"score":0.43181464076042175},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.4312761127948761},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.35048478841781616},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.339627206325531},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.23086422681808472},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.1920395791530609},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.17622220516204834},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.12772083282470703},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.11548653244972229}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isscc.2015.7063021","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isscc.2015.7063021","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W1970092416","https://openalex.org/W1975693956","https://openalex.org/W2006427734","https://openalex.org/W2066100939","https://openalex.org/W2147533202","https://openalex.org/W2171297533"],"related_works":["https://openalex.org/W984417604","https://openalex.org/W2498262093","https://openalex.org/W2474043983","https://openalex.org/W2566880546","https://openalex.org/W2000633969","https://openalex.org/W2544336511","https://openalex.org/W2078513307","https://openalex.org/W1978186604","https://openalex.org/W2144737022","https://openalex.org/W2036880312"],"abstract_inverted_index":{"Phase-locked":[0],"loops":[1],"(PLLs)":[2],"are":[3,51,64,77,100],"a":[4,29,86,92,129,143,169,175,187,198],"crucial":[5],"building":[6],"block":[7],"in":[8,55,58,124],"modern":[9],"Systems-on-Chip":[10],"(SoCs),":[11],"which":[12,151],"contain":[13],"microprocessors,":[14],"I/O":[15],"interfaces,":[16],"memories,":[17],"power":[18],"management,":[19],"and":[20,42,91,98,109,115,120,147,182,186],"communication":[21],"systems.":[22],"Fully":[23],"synthesizable":[24,133,171],"PLLs":[25,50],"[1-2],":[26],"designed":[27],"using":[28],"pure":[30],"digital":[31],"design":[32,40],"flow,":[33],"have":[34],"been":[35],"proposed":[36],"to":[37,53,60,102,117,154],"reduce":[38],"the":[39,74,155,158,192],"cost":[41],"allow":[43],"easier":[44],"integration.":[45],"To":[46],"achieve":[47],"high-frequency":[48],"resolution,":[49,150,185],"required":[52],"operate":[54],"fractional-N":[56,71,172],"mode,":[57],"addition":[59],"integer-N":[61],"mode.":[62],"There":[63],"several":[65],"architectures":[66],"available":[67],"[5-6]":[68],"for":[69,81,132,179,190],"realizing":[70],"operation.":[72],"However,":[73],"existing":[75],"topologies":[76],"not":[78],"well":[79],"suited":[80],"synthesis,":[82],"as":[83],"they":[84],"require":[85],"time-to-digital":[87],"converter":[88,94],"(TDC)":[89],"[3]":[90],"digital-to-time":[93],"(DTC)":[95],"[4-5].":[96],"TDCs":[97],"DTCs":[99],"vulnerable":[101],"layout":[103],"uncertainty,":[104],"arising":[105],"from":[106,138],"automatic":[107],"place":[108],"route":[110],"(P&R),":[111],"introducing":[112],"linearity":[113],"degradation":[114],"leading":[116],"poor":[118],"in-band":[119],"out-of-band":[121],"phase":[122,195],"noise":[123,196],"PLLs.":[125,134],"Injection":[126],"locking":[127],"is":[128,152],"promising":[130],"technique":[131,178],"Unfortunately,":[135],"it":[136],"suffers":[137],"large":[139],"spur":[140],"caused":[141],"by":[142],"periodic":[144],"hard":[145],"refresh,":[146],"limited":[148],"fractional":[149,184],"bounded":[153],"inverse":[156],"of":[157,160],"number":[159],"ring":[161],"oscillator":[162,194],"delay":[163],"stages":[164],"[6].":[165],"This":[166],"paper":[167],"describes":[168],"fully":[170],"PLL":[173],"with":[174],"soft":[176],"injection-locking":[177],"smoothing":[180],"switching":[181],"fine":[183],"cascading":[188],"topology":[189],"suppressing":[191],"free-running":[193],"over":[197],"wide":[199],"loop":[200],"bandwidth.":[201]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":5},{"year":2024,"cited_by_count":3},{"year":2023,"cited_by_count":4},{"year":2022,"cited_by_count":3},{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":4},{"year":2019,"cited_by_count":5},{"year":2018,"cited_by_count":4},{"year":2017,"cited_by_count":5},{"year":2016,"cited_by_count":8},{"year":2015,"cited_by_count":5}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}