{"id":"https://openalex.org/W2080253340","doi":"https://doi.org/10.1109/isscc.2015.7062987","title":"10.5 A 5.9pJ/b 10Gb/s serial link with unequalized MM-CDR in 14nm tri-gate CMOS","display_name":"10.5 A 5.9pJ/b 10Gb/s serial link with unequalized MM-CDR in 14nm tri-gate CMOS","publication_year":2015,"publication_date":"2015-02-01","ids":{"openalex":"https://openalex.org/W2080253340","doi":"https://doi.org/10.1109/isscc.2015.7062987","mag":"2080253340"},"language":"en","primary_location":{"id":"doi:10.1109/isscc.2015.7062987","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isscc.2015.7062987","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5049230596","display_name":"Rajeev Dokania","orcid":"https://orcid.org/0000-0003-0805-2692"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Rajeev Dokania","raw_affiliation_strings":["Intel, Hillsboro, OR"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5037982897","display_name":"Alexandra Kern","orcid":"https://orcid.org/0000-0002-7254-6032"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Alexandra Kern","raw_affiliation_strings":["Intel, Hillsboro, OR"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5114213938","display_name":"Mike He","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Mike He","raw_affiliation_strings":["Intel, Santa Clara, CA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel, Santa Clara, CA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5074396564","display_name":"Adam C. Faust","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Adam Faust","raw_affiliation_strings":["Intel, Hillsboro, OR"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5022506072","display_name":"Richard Tseng","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Richard Tseng","raw_affiliation_strings":["Intel, Hillsboro, OR"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5034543680","display_name":"Skyler Weaver","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Skyler Weaver","raw_affiliation_strings":["Intel, Hillsboro, OR"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5028081514","display_name":"Kai Yu","orcid":"https://orcid.org/0000-0002-0938-2987"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Kai Yu","raw_affiliation_strings":["Intel, Hillsboro, OR"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5067851943","display_name":"Christiaan Bil","orcid":null},"institutions":[{"id":"https://openalex.org/I1330254920","display_name":"Hudson Institute","ror":"https://ror.org/014n3ck53","country_code":"US","type":"nonprofit","lineage":["https://openalex.org/I1330254920"]},{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Christiaan Bil","raw_affiliation_strings":["Intel, Hudson, MA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel, Hudson, MA","institution_ids":["https://openalex.org/I1330254920","https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5060116806","display_name":"Tao Liang","orcid":"https://orcid.org/0000-0003-0634-7948"},"institutions":[{"id":"https://openalex.org/I1330254920","display_name":"Hudson Institute","ror":"https://ror.org/014n3ck53","country_code":"US","type":"nonprofit","lineage":["https://openalex.org/I1330254920"]},{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Tao Liang","raw_affiliation_strings":["Intel, Hudson, MA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel, Hudson, MA","institution_ids":["https://openalex.org/I1330254920","https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5010946517","display_name":"Frank O\u2019Mahony","orcid":"https://orcid.org/0000-0001-7961-9452"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Frank O'Mahony","raw_affiliation_strings":["Intel, Hillsboro, OR"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":48,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"3"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.7387691736221313},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5881156921386719},{"id":"https://openalex.org/keywords/serial-communication","display_name":"Serial communication","score":0.5666483640670776},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5495166778564453},{"id":"https://openalex.org/keywords/baud","display_name":"Baud","score":0.5394855737686157},{"id":"https://openalex.org/keywords/current-mode-logic","display_name":"Current-mode logic","score":0.4516254961490631},{"id":"https://openalex.org/keywords/serdes","display_name":"SerDes","score":0.4401406943798065},{"id":"https://openalex.org/keywords/resistor","display_name":"Resistor","score":0.4300863444805145},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.4247286319732666},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.40788906812667847},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.4071616530418396},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.365492045879364},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.3418794274330139},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.2051415741443634}],"concepts":[{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.7387691736221313},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5881156921386719},{"id":"https://openalex.org/C51707140","wikidata":"https://www.wikidata.org/wiki/Q518280","display_name":"Serial communication","level":2,"score":0.5666483640670776},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5495166778564453},{"id":"https://openalex.org/C169606439","wikidata":"https://www.wikidata.org/wiki/Q192027","display_name":"Baud","level":3,"score":0.5394855737686157},{"id":"https://openalex.org/C2780295579","wikidata":"https://www.wikidata.org/wiki/Q5195108","display_name":"Current-mode logic","level":3,"score":0.4516254961490631},{"id":"https://openalex.org/C19707634","wikidata":"https://www.wikidata.org/wiki/Q6510662","display_name":"SerDes","level":2,"score":0.4401406943798065},{"id":"https://openalex.org/C137488568","wikidata":"https://www.wikidata.org/wiki/Q5321","display_name":"Resistor","level":3,"score":0.4300863444805145},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.4247286319732666},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.40788906812667847},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.4071616530418396},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.365492045879364},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.3418794274330139},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.2051415741443634},{"id":"https://openalex.org/C761482","wikidata":"https://www.wikidata.org/wiki/Q118093","display_name":"Transmission (telecommunications)","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isscc.2015.7062987","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isscc.2015.7062987","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.8600000143051147,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W1982101868","https://openalex.org/W1999903189","https://openalex.org/W2053903285","https://openalex.org/W2104876651","https://openalex.org/W2112857179","https://openalex.org/W4255401592","https://openalex.org/W6836496719"],"related_works":["https://openalex.org/W2379833126","https://openalex.org/W2068643782","https://openalex.org/W2376943082","https://openalex.org/W2361589702","https://openalex.org/W3150743116","https://openalex.org/W2142698693","https://openalex.org/W2206457103","https://openalex.org/W2029675965","https://openalex.org/W2370879924","https://openalex.org/W2358362682"],"abstract_inverted_index":{"High-speed":[0],"serial":[1,77],"links":[2,15,126],"integrated":[3],"in":[4,9,28,53,80],"advanced":[5],"CMOS":[6,83],"are":[7],"ubiquitous":[8],"modern":[10],"microprocessor":[11],"systems.":[12],"These":[13],"commodity":[14],"have":[16],"fixed":[17],"performance":[18],"specs":[19],"and":[20,30,68,109,117,131,182,186],"therefore":[21],"realize":[22,38],"the":[23,46,143,149,153,157,161,170],"benefit":[24],"of":[25,65,94],"technology":[26],"scaling":[27,40],"area":[29],"power":[31],"reduction":[32],"at":[33,127,148,160],"high":[34],"data":[35,129],"rates.":[36],"To":[37],"significant":[39],"benefits,":[41],"these":[42],"designs":[43],"must":[44],"overcome":[45],"challenges":[47],"associated":[48],"with":[49,102,191],"implementing":[50],"analog":[51],"functions":[52],"scaled":[54],"logic-optimized":[55],"processes":[56],"while":[57],"maintaining":[58],"link":[59,78],"robustness":[60],"over":[61],"a":[62,74,95,103,105,110,137,174,184,192],"wide":[63],"range":[64],"channel":[66,132,146],"characteristics":[67],"third":[69],"party":[70],"components.This":[71],"work":[72],"describes":[73],"2.5-to-10":[75],"Gb/s":[76],"implemented":[79],"14nm":[81],"tri-gate":[82],"using":[84,165,178],"logic-pitch":[85],"transistors":[86],"exclusively.":[87],"The":[88],"half-rate":[89],"embedded-clock":[90],"transceiver":[91],"architecture":[92],"consists":[93],"3-tap":[96],"current-mode":[97],"(CM)":[98],"TX,":[99],"an":[100],"RX":[101,188],"CTLE,":[104],"4-tap":[106],"integrating":[107],"DFE,":[108],"phase-interpolator-based":[111],"CDR.":[112],"It":[113,134],"is":[114],"60%":[115],"smaller":[116],"consumes":[118],"11%":[119],"less":[120],"energy":[121],"per":[122],"bit":[123],"than":[124],"reported":[125],"comparable":[128],"rates":[130],"losses.":[133],"also":[135],"introduces":[136],"baud-rate":[138],"CDR":[139],"algorithm":[140],"that":[141],"uses":[142],"real-time":[144],"extracted":[145],"response":[147],"DFE":[150],"to":[151],"optimize":[152],"sampling":[154],"point,":[155],"relaxes":[156],"headroom/swing":[158],"tradeoff":[159],"TX":[162],"driver":[163],"by":[164,177],"dynamic":[166],"signal":[167],"boosting,":[168],"eliminates":[169],"process":[171],"cost":[172],"for":[173],"precision":[175],"resistor":[176],"tunable":[179],"serpentine":[180],"resistors,":[181],"includes":[183],"low-power":[185],"low-area":[187],"squelch":[189],"circuit":[190],"digital":[193],"peak":[194],"detector.":[195]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":5},{"year":2024,"cited_by_count":9},{"year":2023,"cited_by_count":6},{"year":2022,"cited_by_count":6},{"year":2021,"cited_by_count":3},{"year":2020,"cited_by_count":3},{"year":2019,"cited_by_count":5},{"year":2017,"cited_by_count":5},{"year":2016,"cited_by_count":5}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}
