{"id":"https://openalex.org/W2018960859","doi":"https://doi.org/10.1109/isscc.2015.7062934","title":"4.5 The Xeon® processor E5-2600 v3: A 22nm 18-core product family","display_name":"4.5 The Xeon® processor E5-2600 v3: A 22nm 18-core product family","publication_year":2015,"publication_date":"2015-02-01","ids":{"openalex":"https://openalex.org/W2018960859","doi":"https://doi.org/10.1109/isscc.2015.7062934","mag":"2018960859"},"language":"en","primary_location":{"id":"doi:10.1109/isscc.2015.7062934","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isscc.2015.7062934","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5005035025","display_name":"Bill Bowhill","orcid":null},"institutions":[{"id":"https://openalex.org/I4210158342","display_name":"Intel (United Kingdom)","ror":"https://ror.org/058cxws58","country_code":"GB","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210158342"]}],"countries":["GB"],"is_corresponding":true,"raw_author_name":"Bill Bowhill","raw_affiliation_strings":["Intel"],"affiliations":[{"raw_affiliation_string":"Intel","institution_ids":["https://openalex.org/I4210158342"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5075432650","display_name":"Blaine Stackhouse","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Blaine Stackhouse","raw_affiliation_strings":["Intel, Fort Collins, CO"],"affiliations":[{"raw_affiliation_string":"Intel, Fort Collins, CO","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5086217987","display_name":"Nevine Nassif","orcid":null},"institutions":[{"id":"https://openalex.org/I4210158342","display_name":"Intel (United Kingdom)","ror":"https://ror.org/058cxws58","country_code":"GB","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210158342"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Nevine Nassif","raw_affiliation_strings":["Intel"],"affiliations":[{"raw_affiliation_string":"Intel","institution_ids":["https://openalex.org/I4210158342"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5110848656","display_name":"Zibing Yang","orcid":null},"institutions":[{"id":"https://openalex.org/I4210158342","display_name":"Intel (United Kingdom)","ror":"https://ror.org/058cxws58","country_code":"GB","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210158342"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Zibing Yang","raw_affiliation_strings":["Intel"],"affiliations":[{"raw_affiliation_string":"Intel","institution_ids":["https://openalex.org/I4210158342"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5077021882","display_name":"Arvind Raghavan","orcid":"https://orcid.org/0009-0002-5260-1353"},"institutions":[{"id":"https://openalex.org/I4210158342","display_name":"Intel (United Kingdom)","ror":"https://ror.org/058cxws58","country_code":"GB","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210158342"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Arvind Raghavan","raw_affiliation_strings":["Intel"],"affiliations":[{"raw_affiliation_string":"Intel","institution_ids":["https://openalex.org/I4210158342"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5042624329","display_name":"Charles Morganti","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Charles Morganti","raw_affiliation_strings":["Intel, Fort Collins, CO"],"affiliations":[{"raw_affiliation_string":"Intel, Fort Collins, CO","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5044734233","display_name":"Chris Houghton","orcid":null},"institutions":[{"id":"https://openalex.org/I4210158342","display_name":"Intel (United Kingdom)","ror":"https://ror.org/058cxws58","country_code":"GB","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210158342"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Chris Houghton","raw_affiliation_strings":["Intel"],"affiliations":[{"raw_affiliation_string":"Intel","institution_ids":["https://openalex.org/I4210158342"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5044390358","display_name":"Dan Krueger","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Dan Krueger","raw_affiliation_strings":["Intel, Fort Collins, CO"],"affiliations":[{"raw_affiliation_string":"Intel, Fort Collins, CO","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5066591464","display_name":"Olivier Franza","orcid":"https://orcid.org/0009-0007-0803-9064"},"institutions":[{"id":"https://openalex.org/I4210158342","display_name":"Intel (United Kingdom)","ror":"https://ror.org/058cxws58","country_code":"GB","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210158342"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Olivier Franza","raw_affiliation_strings":["Intel"],"affiliations":[{"raw_affiliation_string":"Intel","institution_ids":["https://openalex.org/I4210158342"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5075117369","display_name":"Jayen Desai","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jayen Desai","raw_affiliation_strings":["Intel, Fort Collins, CO"],"affiliations":[{"raw_affiliation_string":"Intel, Fort Collins, CO","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5049223858","display_name":"Jason Crop","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jason Crop","raw_affiliation_strings":["Intel, Fort Collins, CO"],"affiliations":[{"raw_affiliation_string":"Intel, Fort Collins, CO","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5033891765","display_name":"D. K. Bradley","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Dave Bradley","raw_affiliation_strings":["Intel, Fort Collins, CO"],"affiliations":[{"raw_affiliation_string":"Intel, Fort Collins, CO","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5033726603","display_name":"Chris Bostak","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Chris Bostak","raw_affiliation_strings":["Intel, Fort Collins, CO"],"affiliations":[{"raw_affiliation_string":"Intel, Fort Collins, CO","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5071715263","display_name":"Sal Bhimji","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]},{"id":"https://openalex.org/I1330254920","display_name":"Hudson Institute","ror":"https://ror.org/014n3ck53","country_code":"US","type":"nonprofit","lineage":["https://openalex.org/I1330254920"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sal Bhimji","raw_affiliation_strings":["Intel, Hudson, MA"],"affiliations":[{"raw_affiliation_string":"Intel, Hudson, MA","institution_ids":["https://openalex.org/I1330254920","https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5090473722","display_name":"Matt Becker","orcid":null},"institutions":[{"id":"https://openalex.org/I4210158342","display_name":"Intel (United Kingdom)","ror":"https://ror.org/058cxws58","country_code":"GB","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210158342"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Matt Becker","raw_affiliation_strings":["Intel"],"affiliations":[{"raw_affiliation_string":"Intel","institution_ids":["https://openalex.org/I4210158342"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":15,"corresponding_author_ids":["https://openalex.org/A5005035025"],"corresponding_institution_ids":["https://openalex.org/I4210158342"],"apc_list":null,"apc_paid":null,"fwci":4.8447,"has_fulltext":false,"cited_by_count":25,"citation_normalized_percentile":{"value":0.95178877,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"3"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9952999949455261,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/xeon","display_name":"Xeon","score":0.7226713299751282},{"id":"https://openalex.org/keywords/pci-express","display_name":"PCI Express","score":0.5956614017486572},{"id":"https://openalex.org/keywords/voltage-regulator","display_name":"Voltage regulator","score":0.5295661091804504},{"id":"https://openalex.org/keywords/frequency-scaling","display_name":"Frequency scaling","score":0.5295611023902893},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.481444776058197},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.462261825799942},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.4539168179035187},{"id":"https://openalex.org/keywords/pipeline-burst-cache","display_name":"Pipeline burst cache","score":0.4402603209018707},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.4257243871688843},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.41126513481140137},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.3823990821838379},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.3737599849700928},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.3717271089553833},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.35146474838256836},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.34516453742980957},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.18703898787498474},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.1719529628753662}],"concepts":[{"id":"https://openalex.org/C145108525","wikidata":"https://www.wikidata.org/wiki/Q656154","display_name":"Xeon","level":2,"score":0.7226713299751282},{"id":"https://openalex.org/C64270927","wikidata":"https://www.wikidata.org/wiki/Q206924","display_name":"PCI Express","level":3,"score":0.5956614017486572},{"id":"https://openalex.org/C110706871","wikidata":"https://www.wikidata.org/wiki/Q851210","display_name":"Voltage regulator","level":3,"score":0.5295661091804504},{"id":"https://openalex.org/C157742956","wikidata":"https://www.wikidata.org/wiki/Q3237776","display_name":"Frequency scaling","level":3,"score":0.5295611023902893},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.481444776058197},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.462261825799942},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4539168179035187},{"id":"https://openalex.org/C157547923","wikidata":"https://www.wikidata.org/wiki/Q7197276","display_name":"Pipeline burst cache","level":5,"score":0.4402603209018707},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.4257243871688843},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.41126513481140137},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.3823990821838379},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.3737599849700928},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.3717271089553833},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.35146474838256836},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.34516453742980957},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.18703898787498474},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.1719529628753662},{"id":"https://openalex.org/C201148951","wikidata":"https://www.wikidata.org/wiki/Q5015976","display_name":"Cache coloring","level":4,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isscc.2015.7062934","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isscc.2015.7062934","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.8100000023841858}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W1971575710","https://openalex.org/W1990884219","https://openalex.org/W1991991600","https://openalex.org/W2162517322","https://openalex.org/W6683806362"],"related_works":["https://openalex.org/W4293211465","https://openalex.org/W4317356899","https://openalex.org/W77156","https://openalex.org/W2987008052","https://openalex.org/W2064007919","https://openalex.org/W2917675277","https://openalex.org/W1628605343","https://openalex.org/W2237923431","https://openalex.org/W2803972811","https://openalex.org/W2122386578"],"abstract_inverted_index":{"The":[0,30,72,241,250],"next-generation":[1],"enterprise":[2],"Xeon":[3],"server":[4],"processor":[5,31],"maximum":[6],"configuration":[7],"supports":[8,74],"18":[9],"dual-threaded":[10],"64b":[11],"Haswell":[12],"cores,":[13],"45MB":[14],"L3":[15],"cache,":[16],"4":[17],"DDR4-2133MHz":[18],"memory":[19],"channels,":[20],"40":[21],"8GT/s":[22],"PCIe":[23],"lanes,":[24],"and":[25,51,69,89,106,116,164,218,233,243,273],"60":[26],"9.6GT/S":[27],"QPI":[28],"lanes.":[29],"has":[32,126,157],"5.56B":[33],"transistors":[34],"on":[35,57],"a":[36,53,75,128,150,176,191,202,266],"31.9mm\u00d720.8mm":[37],"die":[38,174],"in":[39,190,194,197,259],"Intel's":[40],"high-K":[41],"metal-gate":[42],"tri-gate":[43],"22nm":[44],"CMOS":[45],"technology":[46],"with":[47],"11":[48],"metal":[49,64],"layers":[50,65],"achieves":[52],"33%":[54],"performance":[55,70,272],"boost,":[56],"average,":[58],"over":[59],"previous":[60],"generations.":[61],"Two":[62],"additional":[63],"enable":[66,113],"area":[67],"optimization":[68],"improvement.":[71],"design":[73,82,130,212],"wide":[76,203],"range":[77,206],"of":[78,102,186,207,213,231,237],"configurations,":[79],"including":[80],"thermal":[81],"power":[83,121,142,169,195,248,256],"ranging":[84,91],"from":[85,92,175],"55":[86],"to":[87,94,136,172,265],"165W":[88],"frequencies":[90],"1.6":[93],"3.8GHz.":[95],"Key":[96],"architectural":[97],"innovations":[98],"include":[99],"the":[100,134,173,198,211,214,229,234,260],"addition":[101],"AVX2":[103],"technology,":[104],"DDR4,":[105],"fully":[107,151],"integrated":[108,152],"voltage":[109,153,179,185,205],"regulators":[110],"(FIVR)":[111,156],"that":[112,132,253],"per-core":[114],"p-states":[115],"uncore":[117],"frequency":[118],"scaling.":[119],"Motherboard":[120],"delivery":[122,216],"for":[123],"high-performance":[124],"microprocessors":[125],"become":[127],"significant":[129],"challenge":[131],"threatens":[133],"ability":[135],"cost":[137,225],"effectively":[138],"deliver":[139],"high":[140],"dynamic":[141],"at":[143,182,270],"low":[144],"voltage.":[145],"To":[146],"address":[147],"this":[148],"challenge,":[149],"regulator":[154,180],"solution":[155,269],"been":[158],"implemented,":[159],"which":[160,188,209],"enables":[161,219],"several":[162],"power-performance":[163],"platform":[165,215,255],"optimizations.":[166],"With":[167],"FIVR,":[168],"is":[170,252,257],"delivered":[171],"single":[177],"mother-board":[178],"(MBVR)":[181],"an":[183],"elevated":[184],"1.8V,":[187],"results":[189],"square-law":[192],"reduction":[193],"losses":[196],"platform.":[199],"FIVRs":[200],"have":[201],"input":[204],"\u00b1~200mV":[208],"simplifies":[210],"network":[217],"higher":[220],"MBVR":[221,268],"efficiencies.":[222],"FIVR":[223,261],"delivers":[224],"reductions":[226],"by":[227],"reducing":[228],"number":[230,236],"MBVRs":[232],"total":[235,254],"VR":[238],"phases":[239],"required.":[240],"socket":[242],"package":[244],"also":[245],"require":[246],"fewer":[247],"pins.":[249],"result":[251],"lower":[258],"design,":[262],"when":[263],"compared":[264],"classic":[267],"iso":[271],"cost.":[274]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":5},{"year":2018,"cited_by_count":4},{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":6},{"year":2015,"cited_by_count":3}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}