{"id":"https://openalex.org/W2014357578","doi":"https://doi.org/10.1109/isscc.2012.6176988","title":"A 4.6GHz 162Mb SRAM design in 22nm tri-gate CMOS technology with integrated active V&lt;inf&gt;MIN&lt;/inf&gt;-enhancing assist circuitry","display_name":"A 4.6GHz 162Mb SRAM design in 22nm tri-gate CMOS technology with integrated active V&lt;inf&gt;MIN&lt;/inf&gt;-enhancing assist circuitry","publication_year":2012,"publication_date":"2012-02-01","ids":{"openalex":"https://openalex.org/W2014357578","doi":"https://doi.org/10.1109/isscc.2012.6176988","mag":"2014357578"},"language":"en","primary_location":{"id":"doi:10.1109/isscc.2012.6176988","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isscc.2012.6176988","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 IEEE International Solid-State Circuits Conference","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5053857493","display_name":"Eric Karl","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Eric Karl","raw_affiliation_strings":["Intel, Hillsboro, OR, USA","Intel, Hillsboro OR"],"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel, Hillsboro OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5066037916","display_name":"Yih Wang","orcid":"https://orcid.org/0000-0002-4580-2870"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Yih Wang","raw_affiliation_strings":["Intel, Hillsboro, OR, USA","Intel, Hillsboro OR"],"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel, Hillsboro OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5036589180","display_name":"Yong-Gee Ng","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Yong-Gee Ng","raw_affiliation_strings":["Intel, Hillsboro, OR, USA","Intel, Hillsboro OR"],"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel, Hillsboro OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5007891380","display_name":"Zheng Guo","orcid":"https://orcid.org/0000-0001-8615-9749"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Zheng Guo","raw_affiliation_strings":["Intel, Hillsboro, OR, USA","Intel, Hillsboro OR"],"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel, Hillsboro OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5063387912","display_name":"Fatih Hamzaoglu","orcid":"https://orcid.org/0000-0003-3500-5007"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Fatih Hamzaoglu","raw_affiliation_strings":["Intel, Hillsboro, OR, USA","Intel, Hillsboro OR"],"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel, Hillsboro OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103485789","display_name":"Uddalak Bhattacharya","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Uddalak Bhattacharya","raw_affiliation_strings":["Intel, Hillsboro, OR, USA","Intel, Hillsboro OR"],"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel, Hillsboro OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Kevin Zhang","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Kevin Zhang","raw_affiliation_strings":["Intel, Hillsboro, OR, USA","Intel, Hillsboro OR"],"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel, Hillsboro OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111585700","display_name":"Kaizad Mistry","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Kaizad Mistry","raw_affiliation_strings":["Intel, Hillsboro, OR, USA","Intel, Hillsboro OR"],"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel, Hillsboro OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5029885341","display_name":"M. Bohr","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Mark Bohr","raw_affiliation_strings":["Intel, Hillsboro, OR, USA","Intel, Hillsboro OR"],"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel, Hillsboro OR","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":9,"corresponding_author_ids":["https://openalex.org/A5053857493"],"corresponding_institution_ids":["https://openalex.org/I1343180700"],"apc_list":null,"apc_paid":null,"fwci":14.7308,"has_fulltext":false,"cited_by_count":104,"citation_normalized_percentile":{"value":0.99247445,"is_in_top_1_percent":true,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":90,"max":100},"biblio":{"volume":null,"issue":null,"first_page":"230","last_page":"232"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.6307708621025085},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5799729228019714},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.5102317333221436},{"id":"https://openalex.org/keywords/subthreshold-conduction","display_name":"Subthreshold conduction","score":0.49861955642700195},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.4380730390548706},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.43786951899528503},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.43723371624946594},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.4138423800468445},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.369016170501709},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.3252289593219757},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.27503159642219543}],"concepts":[{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.6307708621025085},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5799729228019714},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.5102317333221436},{"id":"https://openalex.org/C156465305","wikidata":"https://www.wikidata.org/wiki/Q1658601","display_name":"Subthreshold conduction","level":4,"score":0.49861955642700195},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4380730390548706},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.43786951899528503},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.43723371624946594},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.4138423800468445},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.369016170501709},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.3252289593219757},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.27503159642219543}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isscc.2012.6176988","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isscc.2012.6176988","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 IEEE International Solid-State Circuits Conference","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.6299999952316284,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W2024874287","https://openalex.org/W2047956117","https://openalex.org/W2048611611","https://openalex.org/W2095488885","https://openalex.org/W2125347149","https://openalex.org/W2148301792","https://openalex.org/W2165720303","https://openalex.org/W4235474597","https://openalex.org/W4244763807","https://openalex.org/W6656714244"],"related_works":["https://openalex.org/W2806295079","https://openalex.org/W2117824263","https://openalex.org/W3100668214","https://openalex.org/W2134421493","https://openalex.org/W2489257435","https://openalex.org/W1559639976","https://openalex.org/W2009038440","https://openalex.org/W2501578203","https://openalex.org/W2113108952","https://openalex.org/W2040773997"],"abstract_inverted_index":{"Future":[0],"product":[1],"applications":[2],"demand":[3],"increasing":[4],"performance":[5,36,93],"with":[6],"reduced":[7,17],"power":[8],"consumption,":[9],"which":[10],"motivates":[11],"the":[12,44,144,190],"pursuit":[13],"of":[14,116,159,192],"high-performance":[15],"at":[16,94,136],"operating":[18],"voltages.":[19],"Random":[20],"and":[21,34,70,84,123,133,138,170,183],"systematic":[22],"device":[23,92,97],"variations":[24],"pose":[25],"significant":[26],"challenges":[27],"to":[28,43,88,110,196,205],"SRAM":[29,51,150,167,178],"V":[30],"<sub":[31],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[32,64,73,163,174],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">MIN</sub>":[33],"low-voltage":[35,176],"as":[37],"technology":[38,60,79,102],"scaling":[39],"follows":[40],"Moore's":[41],"law":[42],"22nm":[45,57,137],"node.":[46],"A":[47],"high-performance,":[48],"voltage-scalable":[49],"162Mb":[50],"array":[52,202],"is":[53,103],"developed":[54],"in":[55,100,143,201],"a":[56,140,160,171,198],"tri-gate":[58],"bulk":[59],"featuring":[61],"3":[62],"<sup":[63,72,162,173],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">rd</sup>":[65],"-generation":[66,75],"high-k":[67],"metal-gate":[68],"transistors":[69],"5":[71],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">th</sup>":[74],"strained":[76],"silicon.":[77],"Tri-gate":[78],"reduces":[80],"short-channel":[81],"effects":[82],"(SCE)":[83],"improves":[85],"subthreshold":[86],"slope":[87],"provide":[89],"37%":[90],"improved":[91],"0.7V.":[95],"Continuous":[96],"width":[98],"sizing":[99],"planar":[101],"replaced":[104],"by":[105],"combining":[106],"parallel":[107],"silicon":[108],"fins":[109],"multiply":[111],"drive":[112],"current.":[113],"Process-circuit":[114],"co-optimization":[115],"transient":[117],"voltage":[118,146],"collapse":[119],"write":[120],"assist":[121,127],"(TVC-WA)":[122],"wordline":[124],"underdrive":[125],"read":[126],"(WLUD-RA)":[128],"features":[129],"address":[130],"process":[131],"variation":[132],"fin":[134],"quantization":[135],"enable":[139],"175mV":[141],"reduction":[142],"supply":[145],"required":[147],"for":[148],"2GHz":[149],"operation.":[151],"Figure":[152],"13.1.1":[153],"shows":[154],"an":[155],"SEM":[156],"top-down":[157],"view":[158],"0.092\u03bcm":[161],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">2</sup>":[164,175],"high-density":[165],"6T":[166,177],"bitcell":[168],"(HDC)":[169],"0.108\u03bcm":[172],"cell":[179],"(LVC)":[180],"after":[181],"gate":[182],"diffusion":[184],"processing.":[185],"Computational":[186],"OPC/RET":[187],"techniques":[188],"extend":[189],"capabilities":[191],"193nm":[193],"immersion":[194],"lithography":[195],"allow":[197],"1.85\u00d7":[199],"increase":[200],"density":[203],"relative":[204],"32nm":[206],"designs":[207],"[1].":[208]},"counts_by_year":[{"year":2025,"cited_by_count":4},{"year":2024,"cited_by_count":3},{"year":2023,"cited_by_count":2},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":7},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":4},{"year":2017,"cited_by_count":8},{"year":2016,"cited_by_count":12},{"year":2015,"cited_by_count":9},{"year":2014,"cited_by_count":15},{"year":2013,"cited_by_count":24},{"year":2012,"cited_by_count":11}],"updated_date":"2026-04-21T08:09:41.155169","created_date":"2025-10-10T00:00:00"}
