{"id":"https://openalex.org/W2004984689","doi":"https://doi.org/10.1109/isscc.2012.6176966","title":"A 280mV-to-1.1V 256b reconfigurable SIMD vector permutation engine with 2-dimensional shuffle in 22nm CMOS","display_name":"A 280mV-to-1.1V 256b reconfigurable SIMD vector permutation engine with 2-dimensional shuffle in 22nm CMOS","publication_year":2012,"publication_date":"2012-02-01","ids":{"openalex":"https://openalex.org/W2004984689","doi":"https://doi.org/10.1109/isscc.2012.6176966","mag":"2004984689"},"language":"en","primary_location":{"id":"doi:10.1109/isscc.2012.6176966","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isscc.2012.6176966","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 IEEE International Solid-State Circuits Conference","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5109340111","display_name":"Steven Hsu","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Steven Hsu","raw_affiliation_strings":["Intel, Hillsboro, OR, USA","Intel, Hillsboro OR"],"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel, Hillsboro OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5006348328","display_name":"Amit Agarwal","orcid":"https://orcid.org/0000-0002-4220-3346"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Amit Agarwal","raw_affiliation_strings":["Intel, Hillsboro, OR, USA","Intel, Hillsboro OR"],"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel, Hillsboro OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5052106795","display_name":"Mark Anders","orcid":"https://orcid.org/0000-0001-5748-8420"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Mark Anders","raw_affiliation_strings":["Intel, Hillsboro, OR, USA","Intel, Hillsboro OR"],"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel, Hillsboro OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5039276616","display_name":"Sanu Mathew","orcid":"https://orcid.org/0000-0003-1344-7533"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sanu Mathew","raw_affiliation_strings":["Intel, Hillsboro, OR, USA","Intel, Hillsboro OR"],"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel, Hillsboro OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5070239387","display_name":"Himanshu Kaul","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Himanshu Kaul","raw_affiliation_strings":["Intel, Hillsboro, OR, USA","Intel, Hillsboro OR"],"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel, Hillsboro OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5088477949","display_name":"Farhana Sheikh","orcid":"https://orcid.org/0000-0001-5078-0816"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Farhana Sheikh","raw_affiliation_strings":["Intel, Hillsboro, OR, USA","Intel, Hillsboro OR"],"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel, Hillsboro OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5074107306","display_name":"Ram Krishnamurthy","orcid":"https://orcid.org/0000-0002-2428-7099"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ram Krishnamurthy","raw_affiliation_strings":["Intel, Hillsboro, OR, USA","Intel, Hillsboro OR"],"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel, Hillsboro OR","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":7,"corresponding_author_ids":["https://openalex.org/A5109340111"],"corresponding_institution_ids":["https://openalex.org/I1343180700"],"apc_list":null,"apc_paid":null,"fwci":7.6106,"has_fulltext":false,"cited_by_count":55,"citation_normalized_percentile":{"value":0.97626681,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"178","last_page":"180"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11992","display_name":"CCD and CMOS Imaging Sensors","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11992","display_name":"CCD and CMOS Imaging Sensors","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9973000288009644,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9954000115394592,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/register-file","display_name":"Register file","score":0.8051179647445679},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7420942187309265},{"id":"https://openalex.org/keywords/simd","display_name":"SIMD","score":0.6924752593040466},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.6406092643737793},{"id":"https://openalex.org/keywords/crossbar-switch","display_name":"Crossbar switch","score":0.6060201525688171},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.4395192265510559},{"id":"https://openalex.org/keywords/permutation","display_name":"Permutation (music)","score":0.4329744279384613},{"id":"https://openalex.org/keywords/microprocessor","display_name":"Microprocessor","score":0.4116889238357544},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.37128913402557373},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.283983439207077},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.13252100348472595},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.0910511314868927}],"concepts":[{"id":"https://openalex.org/C117280010","wikidata":"https://www.wikidata.org/wiki/Q180944","display_name":"Register file","level":3,"score":0.8051179647445679},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7420942187309265},{"id":"https://openalex.org/C150552126","wikidata":"https://www.wikidata.org/wiki/Q339387","display_name":"SIMD","level":2,"score":0.6924752593040466},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.6406092643737793},{"id":"https://openalex.org/C29984679","wikidata":"https://www.wikidata.org/wiki/Q1929149","display_name":"Crossbar switch","level":2,"score":0.6060201525688171},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.4395192265510559},{"id":"https://openalex.org/C21308566","wikidata":"https://www.wikidata.org/wiki/Q7169365","display_name":"Permutation (music)","level":2,"score":0.4329744279384613},{"id":"https://openalex.org/C2780728072","wikidata":"https://www.wikidata.org/wiki/Q5297","display_name":"Microprocessor","level":2,"score":0.4116889238357544},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.37128913402557373},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.283983439207077},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.13252100348472595},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.0910511314868927},{"id":"https://openalex.org/C24890656","wikidata":"https://www.wikidata.org/wiki/Q82811","display_name":"Acoustics","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isscc.2012.6176966","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isscc.2012.6176966","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 IEEE International Solid-State Circuits Conference","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.9100000262260437,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":4,"referenced_works":["https://openalex.org/W1491082069","https://openalex.org/W1537523419","https://openalex.org/W1966637404","https://openalex.org/W2162991651"],"related_works":["https://openalex.org/W2145932742","https://openalex.org/W2554791727","https://openalex.org/W1874409533","https://openalex.org/W1981395029","https://openalex.org/W3135507399","https://openalex.org/W2108083791","https://openalex.org/W4250137794","https://openalex.org/W2063341228","https://openalex.org/W2069137912","https://openalex.org/W2163611611"],"abstract_inverted_index":{"Energy-efficient":[0],"SIMD":[1,23,54],"permutation":[2,25,56,193],"operations":[3,34],"are":[4],"key":[5],"for":[6,75],"maximizing":[7],"high-performance":[8],"microprocessor":[9],"vector":[10,24,55,155],"datapath":[11],"utilization":[12],"in":[13,80],"multimedia,":[14],"graphics,":[15],"and":[16,96,153,167,257,269],"signal":[17],"processing":[18],"workloads":[19],"[1-3].":[20],"A":[21],"wide":[22,123],"engine":[26,57,194],"is":[27,78],"required":[28],"to":[29,43,52,144,162,227],"achieve":[30],"high-throughput":[31],"data":[32,37],"rearrangement":[33],"on":[35],"large":[36],"sets,":[38],"with":[39,68,101,121,149,230,248,265],"scaled":[40],"supply":[41],"voltages":[42],"deliver":[44],"high":[45],"energy":[46,184,232,267],"efficiency.":[47],"An":[48],"ultra-low-voltage":[49,168],"reconfigurable":[50],"4-way":[51],"32-way":[53],"consisting":[58],"of":[59,127,186,199,213,234,241,274],"a":[60,69,87,122,146,196,259],"32-entry":[61],"\u00d7":[62],"256b":[63,70],"3-read/1-write":[64],"ported":[65],"register":[66,84,110,210,222],"file":[67,85,111,211,223],"byte-wise":[71,136],"any-to-any":[72,141],"permute":[73,130,150,238],"crossbar":[74,131,239],"2-dimensional":[76],"shuffle":[77,89,148],"fabricated":[79],"22nm":[81],"CMOS.":[82],"The":[83,129,192],"integrates":[86],"vertical":[88],"across":[90,118],"multiple":[91],"entries":[92],"into":[93],"read/write":[94],"operations,":[95],"includes":[97,154],"clockless":[98],"static":[99],"reads":[100],"shared":[102,160],"P/N":[103],"dual-ended":[104],"transmission":[105],"gate":[106],"(DETG)":[107],"writes,":[108],"improving":[109,173],"V":[112,175],"<sub":[113,176],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[114,177,202],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">MIN</sub>":[115,178],"by":[116,179],"250mV":[117],"PVT":[119],"variations":[120],"dynamic":[124],"operating":[125],"range":[126],"280mV-1.1V.":[128],"implements":[132],"an":[133,140],"interleaved":[134],"folded":[135],"multiplexer":[137],"layout":[138,198],"forming":[139],"fully-connected":[142],"tree":[143],"perform":[145],"horizontal":[147],"accumulate":[151],"circuits,":[152],"flip-flops,":[156],"stacked":[157],"min-delay":[158],"buffers,":[159],"gates":[161],"average":[163],"min-sized":[164],"transistor":[165],"variation,":[166],"split-output":[169],"(ULVS)":[170],"level":[171],"shifters":[172],"logic":[174],"150mV,":[180],"while":[181,206],"enabling":[182],"peak":[183,231,272],"efficiency":[185,233],"585GOPS/W":[187],"measured":[188,216,225,244,276],"at":[189,217,245,252,277],"260mV,":[190],"50\u00b0C.":[191],"occupies":[195],"dense":[197],"0.048mm":[200],"<sup":[201],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">2</sup>":[203],"(Fig.":[204],"10.1.7)":[205],"achieving:":[207],"(i)":[208],"nominal":[209],"performance":[212,240],"1.8GHz,":[214,278],"106mW":[215],"0.9V,":[218],"50\u00b0C;":[219],"(ii)":[220],"robust":[221],"functionality":[224],"down":[226],"280mV":[228],"(subthreshold)":[229],"154GOPS/W;":[235],"(iii)":[236],"scalable":[237],"2.9GHz,":[242],"69mW":[243],"1.1V,":[246],"50\u00b0C":[247],"deep":[249],"sub-threshold":[250],"operation":[251],"240mV,":[253],"10MHz":[254],"consuming":[255],"19\u03bcW;":[256],"(iv)":[258],"64b":[260],"4\u00d74":[261],"matrix":[262],"transpose":[263],"algorithm":[264],"53%":[266],"savings":[268],"42%":[270],"improved":[271],"throughput":[273],"263Gbps":[275],"0.9V.":[279]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":4},{"year":2019,"cited_by_count":5},{"year":2017,"cited_by_count":5},{"year":2016,"cited_by_count":6},{"year":2015,"cited_by_count":8},{"year":2014,"cited_by_count":7},{"year":2013,"cited_by_count":8},{"year":2012,"cited_by_count":8}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}