{"id":"https://openalex.org/W2024874287","doi":"https://doi.org/10.1109/isscc.2012.6176876","title":"A 22nm IA multi-CPU and GPU System-on-Chip","display_name":"A 22nm IA multi-CPU and GPU System-on-Chip","publication_year":2012,"publication_date":"2012-02-01","ids":{"openalex":"https://openalex.org/W2024874287","doi":"https://doi.org/10.1109/isscc.2012.6176876","mag":"2024874287"},"language":"en","primary_location":{"id":"doi:10.1109/isscc.2012.6176876","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isscc.2012.6176876","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 IEEE International Solid-State Circuits Conference","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5013933634","display_name":"Satish Damaraju","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Satish Damaraju","raw_affiliation_strings":["Intel, Folsom, CA, USA","Intel, Folsom, CA"],"affiliations":[{"raw_affiliation_string":"Intel, Folsom, CA, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel, Folsom, CA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5030038468","display_name":"Varghese George","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Varghese George","raw_affiliation_strings":["Intel, Folsom, CA, USA","Intel, Folsom, CA"],"affiliations":[{"raw_affiliation_string":"Intel, Folsom, CA, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel, Folsom, CA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5045799445","display_name":"Sanjeev Jahagirdar","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sanjeev Jahagirdar","raw_affiliation_strings":["Intel, Folsom, CA, USA","Intel, Folsom, CA"],"affiliations":[{"raw_affiliation_string":"Intel, Folsom, CA, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel, Folsom, CA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5032605532","display_name":"Tanveer Khondker","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Tanveer Khondker","raw_affiliation_strings":["Intel, Folsom, CA, USA","Intel, Folsom, CA"],"affiliations":[{"raw_affiliation_string":"Intel, Folsom, CA, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel, Folsom, CA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5086109201","display_name":"Robert Milstrey","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Robert Milstrey","raw_affiliation_strings":["Intel, Folsom, CA, USA","Intel, Folsom, CA"],"affiliations":[{"raw_affiliation_string":"Intel, Folsom, CA, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel, Folsom, CA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5028725336","display_name":"Sanjib Sarkar","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sanjib Sarkar","raw_affiliation_strings":["Intel, Folsom, CA, USA","Intel, Folsom, CA"],"affiliations":[{"raw_affiliation_string":"Intel, Folsom, CA, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel, Folsom, CA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5031003451","display_name":"Scott Siers","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Scott Siers","raw_affiliation_strings":["Intel, Folsom, CA, USA","Intel, Folsom, CA"],"affiliations":[{"raw_affiliation_string":"Intel, Folsom, CA, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel, Folsom, CA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5025281313","display_name":"Israel Stolero","orcid":null},"institutions":[{"id":"https://openalex.org/I4210104622","display_name":"Intel (Israel)","ror":"https://ror.org/027t2s119","country_code":"IL","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210104622"]}],"countries":["IL"],"is_corresponding":false,"raw_author_name":"Israel Stolero","raw_affiliation_strings":["Intel, Haifa, Israel","Intel, Haifa., Israel"],"affiliations":[{"raw_affiliation_string":"Intel, Haifa, Israel","institution_ids":["https://openalex.org/I4210104622"]},{"raw_affiliation_string":"Intel, Haifa., Israel","institution_ids":["https://openalex.org/I4210104622"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5044133644","display_name":"Arun Subbiah","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Arun Subbiah","raw_affiliation_strings":["Intel, Folsom, CA, USA","Intel, Folsom, CA"],"affiliations":[{"raw_affiliation_string":"Intel, Folsom, CA, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel, Folsom, CA","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":9,"corresponding_author_ids":["https://openalex.org/A5013933634"],"corresponding_institution_ids":["https://openalex.org/I1343180700"],"apc_list":null,"apc_paid":null,"fwci":28.1356,"has_fulltext":false,"cited_by_count":128,"citation_normalized_percentile":{"value":0.99887577,"is_in_top_1_percent":true,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":100},"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.755486249923706},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6118142008781433},{"id":"https://openalex.org/keywords/power-gating","display_name":"Power gating","score":0.5188221335411072},{"id":"https://openalex.org/keywords/pipeline","display_name":"Pipeline (software)","score":0.4698718190193176},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4593622386455536},{"id":"https://openalex.org/keywords/microarchitecture","display_name":"Microarchitecture","score":0.4396919012069702},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.3052319884300232},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.2338450849056244},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.18897032737731934},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.154441237449646},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.14629638195037842}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.755486249923706},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6118142008781433},{"id":"https://openalex.org/C2780700455","wikidata":"https://www.wikidata.org/wiki/Q7236515","display_name":"Power gating","level":4,"score":0.5188221335411072},{"id":"https://openalex.org/C43521106","wikidata":"https://www.wikidata.org/wiki/Q2165493","display_name":"Pipeline (software)","level":2,"score":0.4698718190193176},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4593622386455536},{"id":"https://openalex.org/C107598950","wikidata":"https://www.wikidata.org/wiki/Q259864","display_name":"Microarchitecture","level":2,"score":0.4396919012069702},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.3052319884300232},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.2338450849056244},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.18897032737731934},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.154441237449646},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.14629638195037842}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isscc.2012.6176876","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isscc.2012.6176876","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 IEEE International Solid-State Circuits Conference","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.9100000262260437}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":3,"referenced_works":["https://openalex.org/W1999903189","https://openalex.org/W2098678283","https://openalex.org/W2160574074"],"related_works":["https://openalex.org/W2138099459","https://openalex.org/W2005635288","https://openalex.org/W2140707386","https://openalex.org/W2339195741","https://openalex.org/W1965635593","https://openalex.org/W4210367193","https://openalex.org/W4249785026","https://openalex.org/W2131429702","https://openalex.org/W4254183379","https://openalex.org/W4213166990"],"abstract_inverted_index":{"This":[0],"paper":[1],"describes":[2],"the":[3,36,46,90,104,156,177,180,202,216,252,259,264],"22nm":[4],"Intel\u00ae":[5],"processor":[6,52,208,271],"codenamed":[7],"Ivy":[8,40,235],"Bridge":[9,41,236],"that":[10],"integrates":[11],"up":[12],"to":[13,89,150,164,169,182,187,196,245,257,275,283],"four":[14],"high-performance":[15],"Intel":[16,48],"Architecture":[17],"(IA)":[18],"cores,":[19,178],"a":[20,81,84,127,188,197],"power/performance":[21],"optimized":[22],"graphics/media":[23],"processing":[24],"unit":[25,137],"(GPU),":[26],"as":[27,29,161,163],"well":[28,162],"memory,":[30],"PCIe,":[31],"and":[32,72,100,139,147,153,278],"display":[33,121,130],"controllers":[34],"in":[35,58,61,69,227,281],"same":[37],"die.":[38],"The":[39,51,77,108,132,207,248,270],"architecture":[42],"is":[43,226],"derived":[44],"from":[45],"second-generation":[47],"Core\u2122":[49],"processor.":[50],"has":[53],"about":[54,59],"1.4":[55],"billion":[56],"transistors":[57],"160mm2":[60],"its":[62,75,140,170],"largest":[63],"incarnation.":[64],"It":[65],"introduces":[66],"several":[67,145],"enhancements":[68],"power,":[70],"performance,":[71],"features":[73],"over":[74],"predecessor.":[76,171],"IA":[78],"core":[79,204,232],"adds":[80],"pipelined":[82],"divider,":[83],"next":[85],"page":[86],"prefetcher,":[87],"additions":[88],"ISA":[91],"for":[92,213],"16b":[93],"floating":[94],"point":[95],"conversion,":[96],"fast":[97,101],"string":[98],"moves,":[99],"access":[102],"of":[103,215,268],"FS/GS":[105],"base":[106],"registers.":[107],"Graphics/Media":[109],"block":[110],"provides":[111],"significantly":[112],"improved":[113],"performance":[114,152],"along":[115],"with":[116,126],"DX11":[117],"API":[118],"support.":[119],"Further,":[120],"capabilities":[122],"have":[123,143],"been":[124],"augmented":[125],"third":[128],"independent":[129],"pipeline.":[131],"on-die":[133],"power":[134,146,159,167,211,222,277],"management":[135],"control":[136],"(PCU)":[138],"associated":[141],"firmware":[142],"added":[144],"thermal":[148],"optimizations":[149],"improve":[151,165],"yield":[154],"within":[155],"existing":[157],"platform":[158],"envelopes,":[160],"idle":[166],"relative":[168],"Power":[172],"gates":[173],"are":[174],"distributed":[175],"throughout":[176],"enabling":[179],"PCU":[181,249],"independently":[183],"either":[184],"reduce":[185],"voltage":[186,195],"state":[189],"retention":[190],"voltage,":[191],"or":[192],"turn":[193],"off":[194],"given":[198],"core,":[199],"depending":[200],"on":[201],"current":[203],"usage":[205],"conditions.":[206],"also":[209,250],"implements":[210],"gating":[212],"portions":[214],"DDR":[217],"I/O":[218],"buffers,":[219],"reducing":[220],"CPU":[221],"consumption":[223,280],"when":[224],"memory":[225],"\"self-refresh\"":[228],"mode.":[229],"To":[230],"optimize":[231],"sleep":[233],"time,":[234],"incorporates":[237],"smart":[238],"interrupt":[239],"routing":[240],"logic,":[241],"which":[242],"sends":[243],"interrupts":[244],"active":[246],"cores.":[247],"analyzes":[251],"processor's":[253],"inherent":[254],"voltage-frequency":[255],"dependency":[256],"determine":[258],"optimum":[260],"operating":[261],"voltages":[262],"across":[263],"entire":[265],"dynamic":[266],"range":[267],"operation.":[269],"uses":[272],"die":[273],"temperature":[274],"estimate":[276],"energy":[279],"order":[282],"maximize":[284],"performance.":[285]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":3},{"year":2021,"cited_by_count":3},{"year":2020,"cited_by_count":3},{"year":2019,"cited_by_count":3},{"year":2018,"cited_by_count":7},{"year":2017,"cited_by_count":5},{"year":2016,"cited_by_count":5},{"year":2015,"cited_by_count":16},{"year":2014,"cited_by_count":34},{"year":2013,"cited_by_count":33},{"year":2012,"cited_by_count":14}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
