{"id":"https://openalex.org/W2148769415","doi":"https://doi.org/10.1109/isscc.2011.5746235","title":"A scalable sub-1.2mW 300MHz-to-1.5GHz host-clock PLL for system-on-chip in 32nm CMOS","display_name":"A scalable sub-1.2mW 300MHz-to-1.5GHz host-clock PLL for system-on-chip in 32nm CMOS","publication_year":2011,"publication_date":"2011-02-01","ids":{"openalex":"https://openalex.org/W2148769415","doi":"https://doi.org/10.1109/isscc.2011.5746235","mag":"2148769415"},"language":"en","primary_location":{"id":"doi:10.1109/isscc.2011.5746235","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isscc.2011.5746235","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 IEEE International Solid-State Circuits Conference","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5109317133","display_name":"Hyung\u2010Jin Lee","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Hyung-Jin Lee","raw_affiliation_strings":["Intel, Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5037982897","display_name":"Alexandra Kern","orcid":"https://orcid.org/0000-0002-7254-6032"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Alexandra M. Kern","raw_affiliation_strings":["Intel, Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5018886631","display_name":"Sami Hyvonen","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sami Hyvonen","raw_affiliation_strings":["Intel, Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5073072521","display_name":"Ian A. Young","orcid":"https://orcid.org/0000-0002-4017-5265"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ian A. Young","raw_affiliation_strings":["Intel, Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.3515,"has_fulltext":false,"cited_by_count":12,"citation_normalized_percentile":{"value":0.83649652,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"96","last_page":"97"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9950000047683716,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9934999942779541,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.8525869250297546},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.8504531979560852},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6471266746520996},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.6030041575431824},{"id":"https://openalex.org/keywords/clock-generator","display_name":"Clock generator","score":0.5590533018112183},{"id":"https://openalex.org/keywords/node","display_name":"Node (physics)","score":0.5584166049957275},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5138409733772278},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.512122631072998},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4559611976146698},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.4371234178543091},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.4258500635623932},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.35911762714385986},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2922288775444031},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.1068156361579895}],"concepts":[{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.8525869250297546},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.8504531979560852},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6471266746520996},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.6030041575431824},{"id":"https://openalex.org/C2778023540","wikidata":"https://www.wikidata.org/wiki/Q2164847","display_name":"Clock generator","level":4,"score":0.5590533018112183},{"id":"https://openalex.org/C62611344","wikidata":"https://www.wikidata.org/wiki/Q1062658","display_name":"Node (physics)","level":2,"score":0.5584166049957275},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5138409733772278},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.512122631072998},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4559611976146698},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.4371234178543091},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.4258500635623932},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.35911762714385986},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2922288775444031},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.1068156361579895},{"id":"https://openalex.org/C66938386","wikidata":"https://www.wikidata.org/wiki/Q633538","display_name":"Structural engineering","level":1,"score":0.0},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isscc.2011.5746235","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isscc.2011.5746235","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 IEEE International Solid-State Circuits Conference","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.800000011920929,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":4,"referenced_works":["https://openalex.org/W2064266963","https://openalex.org/W2114953806","https://openalex.org/W2144281377","https://openalex.org/W2147610006"],"related_works":["https://openalex.org/W1994021281","https://openalex.org/W2139484866","https://openalex.org/W2301158783","https://openalex.org/W2369998856","https://openalex.org/W2904837305","https://openalex.org/W2133120878","https://openalex.org/W1969806930","https://openalex.org/W2605831223","https://openalex.org/W2002107209","https://openalex.org/W2376956425"],"abstract_inverted_index":{"System-on-chips":[0],"(SoCs)":[1],"are":[2,10,103],"being":[3],"widely":[4],"adopted":[5],"in":[6,62],"mobile":[7],"applications,":[8],"and":[9,82,88],"driven":[11],"by":[12],"the":[13,27,32,46,74,95,99,107,111,115],"need":[14],"for":[15,31,51,98],"longer":[16],"battery":[17],"life,":[18],"their":[19],"power":[20,42,90,112],"budget":[21],"continues":[22],"to":[23,37,44,73],"decrease.":[24],"In":[25],"addition,":[26],"phase-locked":[28],"loop":[29,83],"(PLL)":[30],"SoC":[33],"host":[34,100],"clock":[35],"has":[36],"be":[38],"a":[39,63],"very":[40],"low":[41],"circuit":[43],"support":[45],"always-on":[47],"always-connected":[48],"(AOAC)":[49],"feature":[50],"SoCs":[52],"integrated":[53],"into":[54],"hand-held":[55],"devices.":[56],"The":[57],"proposed":[58,108],"PLL,":[59],"imple":[60],"mented":[61],"high-k":[64],"metal-gate":[65],"32nm":[66],"logic":[67],"CMOS":[68],"technology,":[69],"provides":[70],"process":[71,76,86],"scalability":[72],"next":[75],"technology":[77],"node,":[78],"uncompromised":[79],"system":[80],"response,":[81],"stability":[84],"under":[85],"variation":[87],"minimum":[89],"envel":[91],"op":[92],"constraints.":[93],"As":[94],"jitter":[96,116],"requirements":[97],"clocking":[101],"PLL":[102],"not":[104],"strin":[105],"gent,":[106],"architecture":[109],"emphasizes":[110],"efficiency":[113],"over":[114],"performance.":[117]},"counts_by_year":[{"year":2022,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2016,"cited_by_count":3},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":2},{"year":2012,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
