{"id":"https://openalex.org/W1993458766","doi":"https://doi.org/10.1109/isscc.2011.5746224","title":"Dynamic hit logic with embedded 8Kb SRAM in 45nm SOI for the zEnterprise&amp;#x2122; processor","display_name":"Dynamic hit logic with embedded 8Kb SRAM in 45nm SOI for the zEnterprise&amp;#x2122; processor","publication_year":2011,"publication_date":"2011-02-01","ids":{"openalex":"https://openalex.org/W1993458766","doi":"https://doi.org/10.1109/isscc.2011.5746224","mag":"1993458766"},"language":"en","primary_location":{"id":"doi:10.1109/isscc.2011.5746224","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isscc.2011.5746224","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 IEEE International Solid-State Circuits Conference","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5000785550","display_name":"A.R. Pelella","orcid":null},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"Antonio R Pelella","raw_affiliation_strings":["IBM Systems and Technology Group, Poughkeepsie, NY, USA","IBM Systems & Technology Group Poughkeepsie, NY"],"affiliations":[{"raw_affiliation_string":"IBM Systems and Technology Group, Poughkeepsie, NY, USA","institution_ids":[]},{"raw_affiliation_string":"IBM Systems & Technology Group Poughkeepsie, NY","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111598082","display_name":"Y.H. Chan","orcid":"https://orcid.org/0009-0004-4911-4233"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Yuen H Chan","raw_affiliation_strings":["IBM Systems and Technology Group, Poughkeepsie, NY, USA","IBM Systems & Technology Group Poughkeepsie, NY"],"affiliations":[{"raw_affiliation_string":"IBM Systems and Technology Group, Poughkeepsie, NY, USA","institution_ids":[]},{"raw_affiliation_string":"IBM Systems & Technology Group Poughkeepsie, NY","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5037696980","display_name":"Bargav Balakrishnan","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Bargav Balakrishnan","raw_affiliation_strings":["IBM Systems and Technology Group, Poughkeepsie, NY, USA","IBM Systems & Technology Group Poughkeepsie, NY"],"affiliations":[{"raw_affiliation_string":"IBM Systems and Technology Group, Poughkeepsie, NY, USA","institution_ids":[]},{"raw_affiliation_string":"IBM Systems & Technology Group Poughkeepsie, NY","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5063894647","display_name":"Pradip Patel","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Pradip Patel","raw_affiliation_strings":["IBM Systems and Technology Group, Poughkeepsie, NY, USA","IBM Systems & Technology Group Poughkeepsie, NY"],"affiliations":[{"raw_affiliation_string":"IBM Systems and Technology Group, Poughkeepsie, NY, USA","institution_ids":[]},{"raw_affiliation_string":"IBM Systems & Technology Group Poughkeepsie, NY","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5037006556","display_name":"D. Rodko","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Daniel Rodko","raw_affiliation_strings":["IBM Systems and Technology Group, Poughkeepsie, NY, USA","IBM Systems & Technology Group Poughkeepsie, NY"],"affiliations":[{"raw_affiliation_string":"IBM Systems and Technology Group, Poughkeepsie, NY, USA","institution_ids":[]},{"raw_affiliation_string":"IBM Systems & Technology Group Poughkeepsie, NY","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5020824665","display_name":"Richard Serton","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Richard E Serton","raw_affiliation_strings":["IBM Systems and Technology Group, Poughkeepsie, NY, USA","IBM Systems & Technology Group Poughkeepsie, NY"],"affiliations":[{"raw_affiliation_string":"IBM Systems and Technology Group, Poughkeepsie, NY, USA","institution_ids":[]},{"raw_affiliation_string":"IBM Systems & Technology Group Poughkeepsie, NY","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5000785550"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.0075,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.76806338,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"72","last_page":"73"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.8122851848602295},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6909143924713135},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5255835652351379},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.5179426074028015},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5010209083557129},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.4702056050300598},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4409661889076233},{"id":"https://openalex.org/keywords/32-bit","display_name":"32-bit","score":0.4138796329498291},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.16170278191566467}],"concepts":[{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.8122851848602295},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6909143924713135},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5255835652351379},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.5179426074028015},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5010209083557129},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4702056050300598},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4409661889076233},{"id":"https://openalex.org/C75695347","wikidata":"https://www.wikidata.org/wiki/Q225147","display_name":"32-bit","level":2,"score":0.4138796329498291},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.16170278191566467}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isscc.2011.5746224","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isscc.2011.5746224","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 IEEE International Solid-State Circuits Conference","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":3,"referenced_works":["https://openalex.org/W1503106634","https://openalex.org/W1996212848","https://openalex.org/W2081726842"],"related_works":["https://openalex.org/W4392590355","https://openalex.org/W3151633427","https://openalex.org/W2212894501","https://openalex.org/W2793465010","https://openalex.org/W3024050170","https://openalex.org/W2375047101","https://openalex.org/W2248357351","https://openalex.org/W1647459083","https://openalex.org/W1979435775","https://openalex.org/W2912838076"],"abstract_inverted_index":{"With":[0],"the":[1,20,82],"push":[2],"to":[3,62,65,95],"ever":[4],"higher":[5],"core":[6],"frequencies,":[7],"more":[8],"logic":[9,36,50,86],"functions":[10],"are":[11],"making":[12],"their":[13],"way":[14],"onto":[15],"critical":[16],"path":[17],"SRAMs":[18],"in":[19,27,44,90,125],"L1":[21],"cache":[22],"look":[23],"up":[24],"structure.":[25],"Described":[26],"this":[28],"paper":[29],"is":[30,104],"a":[31,52,63,107,115,126],"14":[32],"bit":[33,42],"dynamic":[34],"hit":[35,49,85],"scheme":[37,54],"with":[38],"an":[39],"embedded":[40],"8K":[41],"SRAM":[43,83,103,117],"IBM's":[45],"45nm":[46],"SOI.":[47],"The":[48,102],"uses":[51,114],"\"search-for-a-hit\"":[53],"(i.e.,":[55],"XOR's":[56],"followed":[57],"by":[58],"AND":[59],"functions,":[60],"pre-charged":[61],"miss)":[64],"provide":[66],"optimal":[67],"performance,":[68],"timing,":[69],"and":[70,84,99,113],"power.":[71],"A":[72],"custom":[73],"microcode":[74],"programmable":[75],"Array-Built":[76],"-In-Self-Test":[77],"(ABIST)":[78],"engine":[79],"tests":[80],"both":[81],"function":[87],"jointly,":[88],"resulting":[89],"comprehensive":[91],"\"at-speed\"":[92],"test":[93],"coverage":[94],"guarantee":[96],"circuit":[97],"functionality":[98],"timing":[100],"margins.":[101],"organized":[105],"as":[106],"64x15bx8W":[108],"(way,":[109],"or":[110],"set)":[111],"array":[112],"6T":[116],"cell":[118],"(1Read/1Write,":[119],"0.462\u03bcm":[120],"<sup":[121],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[122],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">2</sup>":[123],")":[124],"\"domino\"":[127],"hierarchal":[128],"dual":[129],"read":[130],"bitline":[131],"approach.":[132]},"counts_by_year":[{"year":2017,"cited_by_count":1},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}