{"id":"https://openalex.org/W2098897333","doi":"https://doi.org/10.1109/isscc.2009.4977507","title":"A 2ns-read-latency 4Mb embedded floating-body memory macro in 45nm SOI technology","display_name":"A 2ns-read-latency 4Mb embedded floating-body memory macro in 45nm SOI technology","publication_year":2009,"publication_date":"2009-02-01","ids":{"openalex":"https://openalex.org/W2098897333","doi":"https://doi.org/10.1109/isscc.2009.4977507","mag":"2098897333"},"language":"en","primary_location":{"id":"doi:10.1109/isscc.2009.4977507","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isscc.2009.4977507","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5005502565","display_name":"A.P. Singh","orcid":null},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"Anant Singh","raw_affiliation_strings":["Innovative Silicon, Lausanne, Switzerland"],"affiliations":[{"raw_affiliation_string":"Innovative Silicon, Lausanne, Switzerland","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5031731510","display_name":"Michael Ciraula","orcid":null},"institutions":[{"id":"https://openalex.org/I4210137977","display_name":"Advanced Micro Devices (United States)","ror":"https://ror.org/04kd6c783","country_code":"US","type":"company","lineage":["https://openalex.org/I4210137977"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Michael Ciraula","raw_affiliation_strings":["AMD, Fort Collins, CO, USA","[AMD, Fort Collins, CO, USA]"],"affiliations":[{"raw_affiliation_string":"AMD, Fort Collins, CO, USA","institution_ids":["https://openalex.org/I4210137977"]},{"raw_affiliation_string":"[AMD, Fort Collins, CO, USA]","institution_ids":["https://openalex.org/I4210137977"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5012825824","display_name":"D. Weiss","orcid":null},"institutions":[{"id":"https://openalex.org/I4210137977","display_name":"Advanced Micro Devices (United States)","ror":"https://ror.org/04kd6c783","country_code":"US","type":"company","lineage":["https://openalex.org/I4210137977"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Don Weiss","raw_affiliation_strings":["AMD, Fort Collins, CO, USA","[AMD, Fort Collins, CO, USA]"],"affiliations":[{"raw_affiliation_string":"AMD, Fort Collins, CO, USA","institution_ids":["https://openalex.org/I4210137977"]},{"raw_affiliation_string":"[AMD, Fort Collins, CO, USA]","institution_ids":["https://openalex.org/I4210137977"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5053942589","display_name":"John Wuu","orcid":"https://orcid.org/0009-0009-1998-5536"},"institutions":[{"id":"https://openalex.org/I4210137977","display_name":"Advanced Micro Devices (United States)","ror":"https://ror.org/04kd6c783","country_code":"US","type":"company","lineage":["https://openalex.org/I4210137977"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"John Wuu","raw_affiliation_strings":["AMD, Fort Collins, CO, USA","[AMD, Fort Collins, CO, USA]"],"affiliations":[{"raw_affiliation_string":"AMD, Fort Collins, CO, USA","institution_ids":["https://openalex.org/I4210137977"]},{"raw_affiliation_string":"[AMD, Fort Collins, CO, USA]","institution_ids":["https://openalex.org/I4210137977"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5097231159","display_name":"P. Bauser","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Philippe Bauser","raw_affiliation_strings":["Innovative Silicon, Lausanne, Switzerland"],"affiliations":[{"raw_affiliation_string":"Innovative Silicon, Lausanne, Switzerland","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5097203771","display_name":"P. de Champs","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Paul de Champs","raw_affiliation_strings":["Innovative Silicon, Lausanne, Switzerland"],"affiliations":[{"raw_affiliation_string":"Innovative Silicon, Lausanne, Switzerland","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5097092107","display_name":"H. Daghighian","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Hamid Daghighian","raw_affiliation_strings":["Innovative Silicon, Lausanne, Switzerland"],"affiliations":[{"raw_affiliation_string":"Innovative Silicon, Lausanne, Switzerland","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5075937767","display_name":"David Fisch","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"David Fisch","raw_affiliation_strings":["Innovative Silicon, Lausanne, Switzerland"],"affiliations":[{"raw_affiliation_string":"Innovative Silicon, Lausanne, Switzerland","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5080635239","display_name":"P. Graber","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Philippe Graber","raw_affiliation_strings":["Innovative Silicon, Lausanne, Switzerland"],"affiliations":[{"raw_affiliation_string":"Innovative Silicon, Lausanne, Switzerland","institution_ids":[]}]},{"author_position":"last","author":{"id":null,"display_name":"Michel Bron","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Michel Bron","raw_affiliation_strings":["Innovative Silicon, Lausanne, Switzerland"],"affiliations":[{"raw_affiliation_string":"Innovative Silicon, Lausanne, Switzerland","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":10,"corresponding_author_ids":["https://openalex.org/A5005502565"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":3.9626,"has_fulltext":false,"cited_by_count":15,"citation_normalized_percentile":{"value":0.93715166,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"460","last_page":"461,461a"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/memory-refresh","display_name":"Memory refresh","score":0.7037274241447449},{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.6811483502388},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.6667048931121826},{"id":"https://openalex.org/keywords/non-volatile-random-access-memory","display_name":"Non-volatile random-access memory","score":0.6435163617134094},{"id":"https://openalex.org/keywords/microprocessor","display_name":"Microprocessor","score":0.6319707632064819},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5931037068367004},{"id":"https://openalex.org/keywords/registered-memory","display_name":"Registered memory","score":0.5706678032875061},{"id":"https://openalex.org/keywords/macro","display_name":"Macro","score":0.5547178387641907},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5524908900260925},{"id":"https://openalex.org/keywords/cas-latency","display_name":"CAS latency","score":0.5447748899459839},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.5260574817657471},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.5130237936973572},{"id":"https://openalex.org/keywords/memory-cell","display_name":"Memory cell","score":0.48541197180747986},{"id":"https://openalex.org/keywords/memory-controller","display_name":"Memory controller","score":0.4778801500797272},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.45061907172203064},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.43721821904182434},{"id":"https://openalex.org/keywords/computer-memory","display_name":"Computer memory","score":0.35393527150154114},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.29536211490631104},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1930270493030548},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.10624349117279053},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.07601335644721985}],"concepts":[{"id":"https://openalex.org/C87907426","wikidata":"https://www.wikidata.org/wiki/Q6815755","display_name":"Memory refresh","level":4,"score":0.7037274241447449},{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.6811483502388},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.6667048931121826},{"id":"https://openalex.org/C34172316","wikidata":"https://www.wikidata.org/wiki/Q499024","display_name":"Non-volatile random-access memory","level":5,"score":0.6435163617134094},{"id":"https://openalex.org/C2780728072","wikidata":"https://www.wikidata.org/wiki/Q5297","display_name":"Microprocessor","level":2,"score":0.6319707632064819},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5931037068367004},{"id":"https://openalex.org/C93446704","wikidata":"https://www.wikidata.org/wiki/Q449328","display_name":"Registered memory","level":3,"score":0.5706678032875061},{"id":"https://openalex.org/C166955791","wikidata":"https://www.wikidata.org/wiki/Q629579","display_name":"Macro","level":2,"score":0.5547178387641907},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5524908900260925},{"id":"https://openalex.org/C189930140","wikidata":"https://www.wikidata.org/wiki/Q1112878","display_name":"CAS latency","level":4,"score":0.5447748899459839},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.5260574817657471},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.5130237936973572},{"id":"https://openalex.org/C2776638159","wikidata":"https://www.wikidata.org/wiki/Q18343761","display_name":"Memory cell","level":4,"score":0.48541197180747986},{"id":"https://openalex.org/C100800780","wikidata":"https://www.wikidata.org/wiki/Q1175867","display_name":"Memory controller","level":3,"score":0.4778801500797272},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.45061907172203064},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.43721821904182434},{"id":"https://openalex.org/C92855701","wikidata":"https://www.wikidata.org/wiki/Q5830907","display_name":"Computer memory","level":3,"score":0.35393527150154114},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.29536211490631104},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1930270493030548},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.10624349117279053},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.07601335644721985},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isscc.2009.4977507","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isscc.2009.4977507","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.6399999856948853,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W1568335619","https://openalex.org/W2001044025","https://openalex.org/W2021583529","https://openalex.org/W2062419791","https://openalex.org/W2116633502"],"related_works":["https://openalex.org/W3008068282","https://openalex.org/W2019238062","https://openalex.org/W2557931434","https://openalex.org/W2185658074","https://openalex.org/W4285245242","https://openalex.org/W2132401245","https://openalex.org/W2023569851","https://openalex.org/W1805046480","https://openalex.org/W3089341786","https://openalex.org/W3049130895"],"abstract_inverted_index":{"To":[0],"meet":[1],"advancing":[2],"market":[3],"demands,":[4],"microprocessor":[5,82],"embedded":[6],"memory":[7,13,41,45,62,73,98],"applications":[8],"require":[9],"denser":[10],"and":[11,37,69],"faster":[12],"arrays":[14],"with":[15,28,48],"each":[16],"process":[17],"generation.":[18],"Recent":[19],"work":[20],"presented":[21],"an":[22],"18.5":[23],"ns":[24],"128":[25],"Mb":[26,40,72],"DRAM":[27,35],"a":[29,38,44,56,66,86],"floating":[30,50],"body":[31,51],"cell":[32,46,63],"for":[33],"conventional":[34],"products":[36],"4":[39,71],"macro":[42,74],"using":[43],"built":[47],"two":[49],"transistors.":[52],"This":[53],"paper":[54],"presents":[55],"floating-body":[57],"Z-RAM":[58],"<sup":[59],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[60],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">reg</sup>":[61],"to":[64],"fabricate":[65],"high-density":[67],"low-latency":[68],"high-bandwidth":[70],"building":[75],"block,":[76],"targeted":[77],"at":[78],"the":[79],"requirements":[80],"of":[81],"caches.":[83],"It":[84],"uses":[85],"single":[87],"transistor":[88,96],"(1T),":[89],"unlike":[90],"traditional":[91],"1T1C":[92],"DRAM,":[93],"or":[94],"six":[95],"6T-SRAM":[97],"cell.":[99]},"counts_by_year":[{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":4}],"updated_date":"2026-04-17T18:11:37.981687","created_date":"2025-10-10T00:00:00"}
