{"id":"https://openalex.org/W2095488885","doi":"https://doi.org/10.1109/isscc.2009.4977505","title":"A 4.0 GHz 291Mb voltage-scalable SRAM design in 32nm high-κ metal-gate CMOS with integrated power management","display_name":"A 4.0 GHz 291Mb voltage-scalable SRAM design in 32nm high-κ metal-gate CMOS with integrated power management","publication_year":2009,"publication_date":"2009-02-01","ids":{"openalex":"https://openalex.org/W2095488885","doi":"https://doi.org/10.1109/isscc.2009.4977505","mag":"2095488885"},"language":"en","primary_location":{"id":"doi:10.1109/isscc.2009.4977505","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isscc.2009.4977505","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5066037916","display_name":"Yuxiao Wang","orcid":"https://orcid.org/0009-0004-9454-5972"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Y. Wang","raw_affiliation_strings":["Intel, Hillsboro, OR, USA","[Intel, Hillsboro, OR, USA]"],"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"[Intel, Hillsboro, OR, USA]","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5076211813","display_name":"Uma Bhattacharya","orcid":"https://orcid.org/0000-0001-8677-2156"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"U. Bhattacharya","raw_affiliation_strings":["Intel, Hillsboro, OR, USA","[Intel, Hillsboro, OR, USA]"],"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"[Intel, Hillsboro, OR, USA]","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5063387912","display_name":"Fatih Hamzaoglu","orcid":"https://orcid.org/0000-0003-3500-5007"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"F. Hamzaoglu","raw_affiliation_strings":["Intel, Hillsboro, OR, USA","[Intel, Hillsboro, OR, USA]"],"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"[Intel, Hillsboro, OR, USA]","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5108472270","display_name":"P. Kolar","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"P. Kolar","raw_affiliation_strings":["Intel, Hillsboro, OR, USA","[Intel, Hillsboro, OR, USA]"],"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"[Intel, Hillsboro, OR, USA]","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5019496095","display_name":"Yat Hon Ng","orcid":"https://orcid.org/0000-0001-7400-6948"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Y. Ng","raw_affiliation_strings":["Intel, Hillsboro, OR, USA","[Intel, Hillsboro, OR, USA]"],"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"[Intel, Hillsboro, OR, USA]","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5090064960","display_name":"Lili Wei","orcid":"https://orcid.org/0000-0002-2428-4111"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"L. Wei","raw_affiliation_strings":["Intel, Hillsboro, OR, USA","[Intel, Hillsboro, OR, USA]"],"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"[Intel, Hillsboro, OR, USA]","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5107094038","display_name":"Yu Zhang","orcid":"https://orcid.org/0009-0005-2104-5421"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Y. Zhang","raw_affiliation_strings":["Intel, Hillsboro, OR, USA","[Intel, Hillsboro, OR, USA]"],"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"[Intel, Hillsboro, OR, USA]","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101619626","display_name":"Kedong Zhang","orcid":"https://orcid.org/0000-0001-6801-5928"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"K. Zhang","raw_affiliation_strings":["Intel, Hillsboro, OR, USA","[Intel, Hillsboro, OR, USA]"],"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"[Intel, Hillsboro, OR, USA]","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5029885341","display_name":"M. Bohr","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"M. Bohr","raw_affiliation_strings":["Intel, Hillsboro, OR, USA","[Intel, Hillsboro, OR, USA]"],"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"[Intel, Hillsboro, OR, USA]","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":9,"corresponding_author_ids":["https://openalex.org/A5066037916"],"corresponding_institution_ids":["https://openalex.org/I1343180700"],"apc_list":null,"apc_paid":null,"fwci":6.5797,"has_fulltext":false,"cited_by_count":41,"citation_normalized_percentile":{"value":0.96991677,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"456","last_page":"457,457a"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.832197904586792},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.7020706534385681},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.6419782042503357},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.5725474953651428},{"id":"https://openalex.org/keywords/leakage","display_name":"Leakage (economics)","score":0.5608810782432556},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5018994808197021},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.47260338068008423},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.46783649921417236},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.45007872581481934},{"id":"https://openalex.org/keywords/threshold-voltage","display_name":"Threshold voltage","score":0.440862774848938},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.35976383090019226},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.3512387275695801}],"concepts":[{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.832197904586792},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.7020706534385681},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.6419782042503357},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.5725474953651428},{"id":"https://openalex.org/C2777042071","wikidata":"https://www.wikidata.org/wiki/Q6509304","display_name":"Leakage (economics)","level":2,"score":0.5608810782432556},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5018994808197021},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.47260338068008423},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.46783649921417236},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.45007872581481934},{"id":"https://openalex.org/C195370968","wikidata":"https://www.wikidata.org/wiki/Q1754002","display_name":"Threshold voltage","level":4,"score":0.440862774848938},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.35976383090019226},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.3512387275695801},{"id":"https://openalex.org/C139719470","wikidata":"https://www.wikidata.org/wiki/Q39680","display_name":"Macroeconomics","level":1,"score":0.0},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isscc.2009.4977505","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isscc.2009.4977505","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.4399999976158142,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W2002612140","https://openalex.org/W2033077089","https://openalex.org/W2041626447","https://openalex.org/W2096046678","https://openalex.org/W2096142955","https://openalex.org/W2126898248"],"related_works":["https://openalex.org/W3151633427","https://openalex.org/W2212894501","https://openalex.org/W2793465010","https://openalex.org/W3024050170","https://openalex.org/W4293253840","https://openalex.org/W4378977321","https://openalex.org/W2967161359","https://openalex.org/W4241238243","https://openalex.org/W2501578203","https://openalex.org/W2113108952"],"abstract_inverted_index":{"CMOS":[0,85],"technology":[1],"has":[2],"followed":[3],"Moore's":[4],"law":[5],"into":[6],"the":[7,29,35,43,59,96,105,126,131],"nanoscale":[8],"regime":[9],"where":[10],"SRAM":[11,50,62,79,108,179],"scaling":[12,60,147],"is":[13,110],"facing":[14],"increasing":[15,44],"challenges":[16],"in":[17,31,49,57,81,116,148,175],"gaining":[18],"performance":[19,99],"at":[20,130],"reduced":[21],"leakage":[22,72,166,180],"power":[23,160],"for":[24],"future":[25],"product":[26],"applications.":[27,153],"Despite":[28],"advances":[30],"process":[32],"technologies":[33],"and":[34,71,91,101,118,151,170],"resultant":[36],"ability":[37],"to":[38,112,125,143],"produce":[39],"ever-smaller":[40],"feature":[41],"sizes,":[42],"variations":[45],"of":[46,61,140,178],"scaled":[47],"devices":[48],"are":[51],"playing":[52],"an":[53,158],"increasingly":[54],"important":[55],"role":[56],"determining":[58],"operating":[63,141],"voltage":[64,146],"(V":[65],"cc":[68],"),":[69],"frequency":[70],"power.":[73],"We":[74],"develop":[75],"a":[76,137],"high-performance":[77,150],"voltage-scalable":[78],"design":[80,109,129,135,155],"32":[82,106],"nm":[83,107,128],"logic":[84],"featuring":[86],"2nd-generation":[87],"high-k":[88],"metal-gate":[89],"transistors":[90],"4th-generation":[92],"strained":[93],"silicon.":[94],"With":[95],"continued":[97],"transistor":[98],"enhancement":[100],"extensive":[102],"process-circuit":[103],"co-optimization,":[104],"able":[111],"achieve":[113],"2times":[114],"improvement":[115],"density":[117],"15%":[119],"faster":[120],"access":[121],"speed":[122],"when":[123],"compared":[124],"45":[127],"same":[132],"voltage.":[133],"The":[134,154],"supports":[136],"broad":[138],"range":[139],"voltages":[142],"enable":[144],"dynamic":[145],"today's":[149],"low-power":[152],"also":[156],"features":[157],"integrated":[159],"management":[161],"scheme":[162],"with":[163],"close-loop":[164],"array":[165],"control,":[167],"floating":[168],"bitline":[169],"wordline":[171],"driver":[172],"sleep,":[173],"resulting":[174],"58%":[176],"reduction":[177],"consumption.":[181]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2014,"cited_by_count":10},{"year":2013,"cited_by_count":5},{"year":2012,"cited_by_count":4}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}