{"id":"https://openalex.org/W2168359827","doi":"https://doi.org/10.1109/isscc.2009.4977458","title":"A 40Gb/s full-rate 2:1 MUX in 0.18µm CMOS","display_name":"A 40Gb/s full-rate 2:1 MUX in 0.18µm CMOS","publication_year":2009,"publication_date":"2009-02-01","ids":{"openalex":"https://openalex.org/W2168359827","doi":"https://doi.org/10.1109/isscc.2009.4977458","mag":"2168359827"},"language":"en","primary_location":{"id":"doi:10.1109/isscc.2009.4977458","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isscc.2009.4977458","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5110036907","display_name":"A. Yazdi","orcid":null},"institutions":[{"id":"https://openalex.org/I204250578","display_name":"University of California, Irvine","ror":"https://ror.org/04gyf1771","country_code":"US","type":"education","lineage":["https://openalex.org/I204250578"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"A. Yazdi","raw_affiliation_strings":["University of California, Irvine, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of California, Irvine, CA, USA","institution_ids":["https://openalex.org/I204250578"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5079946016","display_name":"M.M. Green","orcid":null},"institutions":[{"id":"https://openalex.org/I204250578","display_name":"University of California, Irvine","ror":"https://ror.org/04gyf1771","country_code":"US","type":"education","lineage":["https://openalex.org/I204250578"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"M.M. Green","raw_affiliation_strings":["University of California, Irvine, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of California, Irvine, CA, USA","institution_ids":["https://openalex.org/I204250578"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I204250578"],"apc_list":null,"apc_paid":null,"fwci":0.9156,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.7893063,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"362","last_page":"363,363a"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11429","display_name":"Semiconductor Lasers and Optical Devices","score":0.998199999332428,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/multiplexer","display_name":"Multiplexer","score":0.8889756202697754},{"id":"https://openalex.org/keywords/retiming","display_name":"Retiming","score":0.802762508392334},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.7751543521881104},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.759723424911499},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6127688884735107},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5664183497428894},{"id":"https://openalex.org/keywords/block","display_name":"Block (permutation group theory)","score":0.4879131019115448},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4770345389842987},{"id":"https://openalex.org/keywords/clock-recovery","display_name":"Clock recovery","score":0.43016886711120605},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.3531743884086609},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.3468220829963684},{"id":"https://openalex.org/keywords/multiplexing","display_name":"Multiplexing","score":0.3419491648674011},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.21731889247894287},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.20062527060508728}],"concepts":[{"id":"https://openalex.org/C70970002","wikidata":"https://www.wikidata.org/wiki/Q189434","display_name":"Multiplexer","level":3,"score":0.8889756202697754},{"id":"https://openalex.org/C41112130","wikidata":"https://www.wikidata.org/wiki/Q2146175","display_name":"Retiming","level":2,"score":0.802762508392334},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.7751543521881104},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.759723424911499},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6127688884735107},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5664183497428894},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.4879131019115448},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4770345389842987},{"id":"https://openalex.org/C2779835379","wikidata":"https://www.wikidata.org/wiki/Q2348121","display_name":"Clock recovery","level":4,"score":0.43016886711120605},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.3531743884086609},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.3468220829963684},{"id":"https://openalex.org/C19275194","wikidata":"https://www.wikidata.org/wiki/Q222903","display_name":"Multiplexing","level":2,"score":0.3419491648674011},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.21731889247894287},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.20062527060508728},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isscc.2009.4977458","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isscc.2009.4977458","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.7200000286102295,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":21,"referenced_works":["https://openalex.org/W1510418700","https://openalex.org/W1585642076","https://openalex.org/W1983414788","https://openalex.org/W1993254104","https://openalex.org/W1995555774","https://openalex.org/W2007905475","https://openalex.org/W2012743477","https://openalex.org/W2016598672","https://openalex.org/W2034525900","https://openalex.org/W2056693201","https://openalex.org/W2104769399","https://openalex.org/W2110067891","https://openalex.org/W2115431377","https://openalex.org/W2133616438","https://openalex.org/W2138467749","https://openalex.org/W2147646904","https://openalex.org/W2147938149","https://openalex.org/W2161314845","https://openalex.org/W2165893215","https://openalex.org/W2168035478","https://openalex.org/W2538932430"],"related_works":["https://openalex.org/W2018253456","https://openalex.org/W1989584505","https://openalex.org/W1991308997","https://openalex.org/W99106843","https://openalex.org/W2181640182","https://openalex.org/W2554461666","https://openalex.org/W1574257586","https://openalex.org/W3140425496","https://openalex.org/W1558757026","https://openalex.org/W1565428738"],"abstract_inverted_index":{"Serial":[0],"data":[1,21,31,90],"communication":[2,32],"systems":[3],"operating":[4],"at":[5,48],"throughputs":[6],"of":[7,50,57,87,94],"40":[8,51,88,95],"Gb/s":[9,52,89],"have":[10,38,61],"been":[11,39,62],"developed":[12],"in":[13,28,41,71],"recent":[14],"years":[15],"to":[16,73],"increase":[17],"transmission":[18],"capacity.":[19],"A":[20,65],"multiplexer":[22],"(MUX)":[23],"is":[24],"a":[25],"key":[26],"block":[27],"any":[29],"high-speed":[30,81],"system.":[33],"Several":[34],"4:1":[35],"MUX":[36,59],"circuits":[37,60],"reported":[40],"technologies":[42],"such":[43],"as":[44],"SiGe,":[45],"GaAsand":[46],"InP":[47],"speeds":[49],"or":[53],"higher.":[54],"CMOS":[55],"implementations":[56],"half-rate":[58],"also":[63],"reported.":[64],"full-rate":[66],"architecture":[67],"would":[68],"be":[69],"desirable":[70],"order":[72],"reduce":[74],"the":[75],"deterministic":[76],"jitter.":[77],"This":[78],"paper":[79],"describes":[80],"design":[82],"techniques":[83],"used":[84],"for":[85],"retiming":[86],"signals":[91],"and":[92],"generation":[93],"GHz":[96],"clock":[97],"signals.":[98]},"counts_by_year":[{"year":2016,"cited_by_count":1},{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2026-06-26T08:34:08.712188","created_date":"2025-10-10T00:00:00"}