{"id":"https://openalex.org/W2056148264","doi":"https://doi.org/10.1109/isscc.2009.4977312","title":"Over one million TPCC with a 45nm 6-core Xeon&amp;#x00AE; CPU","display_name":"Over one million TPCC with a 45nm 6-core Xeon&amp;#x00AE; CPU","publication_year":2009,"publication_date":"2009-02-01","ids":{"openalex":"https://openalex.org/W2056148264","doi":"https://doi.org/10.1109/isscc.2009.4977312","mag":"2056148264"},"language":"en","primary_location":{"id":"doi:10.1109/isscc.2009.4977312","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isscc.2009.4977312","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5060198356","display_name":"R. Kuppuswamy","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]},{"id":"https://openalex.org/I4210146682","display_name":"Intel (India)","ror":"https://ror.org/04f2n1245","country_code":"IN","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210146682"]}],"countries":["IN","US"],"is_corresponding":true,"raw_author_name":"R. Kuppuswamy","raw_affiliation_strings":["Intel Corporation, Bangalore, India","[Intel, Bangalore, India]"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, Bangalore, India","institution_ids":["https://openalex.org/I4210146682"]},{"raw_affiliation_string":"[Intel, Bangalore, India]","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5110286998","display_name":"S.R. Sawant","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]},{"id":"https://openalex.org/I4210146682","display_name":"Intel (India)","ror":"https://ror.org/04f2n1245","country_code":"IN","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210146682"]}],"countries":["IN","US"],"is_corresponding":false,"raw_author_name":"S.R. Sawant","raw_affiliation_strings":["Intel Corporation, Bangalore, India","[Intel, Bangalore, India]"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, Bangalore, India","institution_ids":["https://openalex.org/I4210146682"]},{"raw_affiliation_string":"[Intel, Bangalore, India]","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5030571689","display_name":"Sundaravadivel Balasubramanian","orcid":"https://orcid.org/0000-0002-2719-4541"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]},{"id":"https://openalex.org/I4210146682","display_name":"Intel (India)","ror":"https://ror.org/04f2n1245","country_code":"IN","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210146682"]}],"countries":["IN","US"],"is_corresponding":false,"raw_author_name":"S. Balasubramanian","raw_affiliation_strings":["Intel Corporation, Bangalore, India","[Intel, Bangalore, India]"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, Bangalore, India","institution_ids":["https://openalex.org/I4210146682"]},{"raw_affiliation_string":"[Intel, Bangalore, India]","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5044843602","display_name":"P. Kaushik","orcid":null},"institutions":[{"id":"https://openalex.org/I4210146682","display_name":"Intel (India)","ror":"https://ror.org/04f2n1245","country_code":"IN","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210146682"]},{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["IN","US"],"is_corresponding":false,"raw_author_name":"P. Kaushik","raw_affiliation_strings":["Intel Corporation, Bangalore, India","[Intel, Bangalore, India]"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, Bangalore, India","institution_ids":["https://openalex.org/I4210146682"]},{"raw_affiliation_string":"[Intel, Bangalore, India]","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5017175274","display_name":"Nagarajan Natarajan","orcid":"https://orcid.org/0000-0001-6435-245X"},"institutions":[{"id":"https://openalex.org/I4210146682","display_name":"Intel (India)","ror":"https://ror.org/04f2n1245","country_code":"IN","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210146682"]},{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["IN","US"],"is_corresponding":false,"raw_author_name":"N. Natarajan","raw_affiliation_strings":["Intel Corporation, Bangalore, India","[Intel, Bangalore, India]"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, Bangalore, India","institution_ids":["https://openalex.org/I4210146682"]},{"raw_affiliation_string":"[Intel, Bangalore, India]","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5109168665","display_name":"J.D. Gilbert","orcid":null},"institutions":[{"id":"https://openalex.org/I4210146682","display_name":"Intel (India)","ror":"https://ror.org/04f2n1245","country_code":"IN","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210146682"]},{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["IN","US"],"is_corresponding":false,"raw_author_name":"J.D. Gilbert","raw_affiliation_strings":["Intel Corporation, Bangalore, India","[Intel, Bangalore, India]"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, Bangalore, India","institution_ids":["https://openalex.org/I4210146682"]},{"raw_affiliation_string":"[Intel, Bangalore, India]","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5060198356"],"corresponding_institution_ids":["https://openalex.org/I1343180700","https://openalex.org/I4210146682"],"apc_list":null,"apc_paid":null,"fwci":1.8467,"has_fulltext":false,"cited_by_count":16,"citation_normalized_percentile":{"value":0.85781944,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":"12","issue":null,"first_page":"70","last_page":"71,71a"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9975000023841858,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9973999857902527,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5206500887870789},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.5175673365592957},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.4948098063468933},{"id":"https://openalex.org/keywords/xeon","display_name":"Xeon","score":0.4803703725337982},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.4692012667655945},{"id":"https://openalex.org/keywords/server","display_name":"Server","score":0.46498414874076843},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.4580172598361969},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.4524790048599243},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.4210279881954193},{"id":"https://openalex.org/keywords/interface","display_name":"Interface (matter)","score":0.411082923412323},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3714723587036133},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.32792067527770996},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2607883810997009},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.23343819379806519},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.15386101603507996}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5206500887870789},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.5175673365592957},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.4948098063468933},{"id":"https://openalex.org/C145108525","wikidata":"https://www.wikidata.org/wiki/Q656154","display_name":"Xeon","level":2,"score":0.4803703725337982},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.4692012667655945},{"id":"https://openalex.org/C93996380","wikidata":"https://www.wikidata.org/wiki/Q44127","display_name":"Server","level":2,"score":0.46498414874076843},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.4580172598361969},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.4524790048599243},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.4210279881954193},{"id":"https://openalex.org/C113843644","wikidata":"https://www.wikidata.org/wiki/Q901882","display_name":"Interface (matter)","level":4,"score":0.411082923412323},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3714723587036133},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.32792067527770996},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2607883810997009},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.23343819379806519},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.15386101603507996},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0},{"id":"https://openalex.org/C157915830","wikidata":"https://www.wikidata.org/wiki/Q2928001","display_name":"Bubble","level":2,"score":0.0},{"id":"https://openalex.org/C129307140","wikidata":"https://www.wikidata.org/wiki/Q6795880","display_name":"Maximum bubble pressure method","level":3,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isscc.2009.4977312","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isscc.2009.4977312","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.6800000071525574,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":1,"referenced_works":["https://openalex.org/W2001894083"],"related_works":["https://openalex.org/W1615383022","https://openalex.org/W2340180648","https://openalex.org/W2103667109","https://openalex.org/W2022666014","https://openalex.org/W2995515486","https://openalex.org/W2079303253","https://openalex.org/W2085237598","https://openalex.org/W2159870643","https://openalex.org/W2113124081","https://openalex.org/W4238719002"],"abstract_inverted_index":{"This":[0],"paper":[1],"describes":[2],"the":[3,60,64,67],"6-core":[4],"Xeonreg":[5],"7400":[6],"series":[7],"processor":[8,23,91],"family,":[9],"code-name":[10],"Dunnington,":[11],"designed":[12],"for":[13],"a":[14,35,45],"broad":[15],"range":[16],"of":[17,25,66],"highly":[18],"power":[19,115],"efficient":[20],"servers.":[21],"The":[22,53,69,80,90,111],"consists":[24],"three":[26],"dual-core":[27],"45nm":[28,100],"Core":[29],"<sup":[30,49],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[31,50],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">TM</sup>":[32],"processors":[33],"and":[34,86,96,106],"shared":[36],"inclusive":[37],"16":[38],"MB":[39],"L3":[40],"cache":[41],"(LLC)":[42],"integrated":[43],"on":[44],"monolithic":[46],"503":[47],"mm":[48],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">2</sup>":[51],"die.":[52,68],"system":[54],"interface":[55],"is":[56,72,97,116],"FSB":[57],"based":[58],"with":[59,74],"l/Os":[61],"incorporated":[62],"into":[63],"center":[65],"core-to-FSB":[70],"connection":[71],"replaced":[73],"an":[75],"on-die":[76],"low-latency":[77],"uncore":[78,81],"interface.":[79],"arbitrates":[82],"among":[83],"core,":[84],"LLC,":[85],"external":[87],"bus":[88],"requests.":[89],"has":[92],"1.9":[93],"B":[94],"transistors":[95,105],"implemented":[98],"in":[99],"CMOS":[101],"using":[102],"high-kappa":[103],"metal-gate":[104],"nine":[107],"copper":[108],"interconnect":[109],"layers.":[110],"maximum":[112],"thermal":[113],"design":[114],"130":[117],"W.":[118]},"counts_by_year":[{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":1},{"year":2018,"cited_by_count":3},{"year":2015,"cited_by_count":1},{"year":2013,"cited_by_count":2},{"year":2012,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}