{"id":"https://openalex.org/W2044141477","doi":"https://doi.org/10.1109/isscc.2009.4977308","title":"Dynamic frequency-switching clock system on a quad-core Itanium&amp;#x00AE; processor","display_name":"Dynamic frequency-switching clock system on a quad-core Itanium&amp;#x00AE; processor","publication_year":2009,"publication_date":"2009-02-01","ids":{"openalex":"https://openalex.org/W2044141477","doi":"https://doi.org/10.1109/isscc.2009.4977308","mag":"2044141477"},"language":"en","primary_location":{"id":"doi:10.1109/isscc.2009.4977308","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isscc.2009.4977308","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5111736771","display_name":"A.J. Allen","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"A. Allen","raw_affiliation_strings":["Intel, Fort Collins, CO, USA"],"affiliations":[{"raw_affiliation_string":"Intel, Fort Collins, CO, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5051843374","display_name":"J. Desai","orcid":"https://orcid.org/0000-0001-5316-1471"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"J. Desai","raw_affiliation_strings":["Intel, Fort Collins, CO, USA"],"affiliations":[{"raw_affiliation_string":"Intel, Fort Collins, CO, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5038953549","display_name":"Frank Verdico","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"F. Verdico","raw_affiliation_strings":["Intel, Fort Collins, CO, USA"],"affiliations":[{"raw_affiliation_string":"Intel, Fort Collins, CO, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5091315712","display_name":"F.E. Anderson","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"F. Anderson","raw_affiliation_strings":["Intel, Fort Collins, CO, USA"],"affiliations":[{"raw_affiliation_string":"Intel, Fort Collins, CO, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5081673969","display_name":"David R. Mulvihill","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"D. Mulvihill","raw_affiliation_strings":["Intel, Fort Collins, CO, USA"],"affiliations":[{"raw_affiliation_string":"Intel, Fort Collins, CO, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5044390358","display_name":"Dan Krueger","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"D. Krueger","raw_affiliation_strings":["Intel, Fort Collins, CO, USA"],"affiliations":[{"raw_affiliation_string":"Intel, Fort Collins, CO, USA","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5111736771"],"corresponding_institution_ids":["https://openalex.org/I1343180700"],"apc_list":null,"apc_paid":null,"fwci":2.0935,"has_fulltext":false,"cited_by_count":20,"citation_normalized_percentile":{"value":0.87243115,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"62","last_page":"63,63a"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11429","display_name":"Semiconductor Lasers and Optical Devices","score":0.9952999949455261,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9947999715805054,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.7567880153656006},{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.6692818403244019},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.553003191947937},{"id":"https://openalex.org/keywords/clock-synchronization","display_name":"Clock synchronization","score":0.5085488557815552},{"id":"https://openalex.org/keywords/cpu-multiplier","display_name":"CPU multiplier","score":0.4736042022705078},{"id":"https://openalex.org/keywords/clock-domain-crossing","display_name":"Clock domain crossing","score":0.41787824034690857},{"id":"https://openalex.org/keywords/synchronization","display_name":"Synchronization (alternating current)","score":0.2601638436317444},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.2514354884624481},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.22789546847343445},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.16639810800552368},{"id":"https://openalex.org/keywords/channel","display_name":"Channel (broadcasting)","score":0.07785296440124512}],"concepts":[{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.7567880153656006},{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.6692818403244019},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.553003191947937},{"id":"https://openalex.org/C129891060","wikidata":"https://www.wikidata.org/wiki/Q1513059","display_name":"Clock synchronization","level":4,"score":0.5085488557815552},{"id":"https://openalex.org/C125576049","wikidata":"https://www.wikidata.org/wiki/Q2246273","display_name":"CPU multiplier","level":5,"score":0.4736042022705078},{"id":"https://openalex.org/C127204226","wikidata":"https://www.wikidata.org/wiki/Q5134799","display_name":"Clock domain crossing","level":5,"score":0.41787824034690857},{"id":"https://openalex.org/C2778562939","wikidata":"https://www.wikidata.org/wiki/Q1298791","display_name":"Synchronization (alternating current)","level":3,"score":0.2601638436317444},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.2514354884624481},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.22789546847343445},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.16639810800552368},{"id":"https://openalex.org/C127162648","wikidata":"https://www.wikidata.org/wiki/Q16858953","display_name":"Channel (broadcasting)","level":2,"score":0.07785296440124512}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isscc.2009.4977308","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isscc.2009.4977308","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.8399999737739563}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W1514437667","https://openalex.org/W2096805904","https://openalex.org/W2116295078","https://openalex.org/W2118565267","https://openalex.org/W2172440946"],"related_works":["https://openalex.org/W1480586493","https://openalex.org/W1842357617","https://openalex.org/W366862498","https://openalex.org/W1781170684","https://openalex.org/W2285301449","https://openalex.org/W2082030077","https://openalex.org/W2189582874","https://openalex.org/W2150865404","https://openalex.org/W3113336138","https://openalex.org/W2153743315"],"abstract_inverted_index":{"The700mm":[0],"<sup":[1,6,22],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[2,7,23],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">2</sup>":[3],"65nm":[4],"Itanium":[5],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">reg</sup>":[8,24],"processor":[9],"codenamed":[10],"Tukwila":[11],"integrates":[12],"four":[13,28],"cores":[14],"and":[15,27,35,54,88,107],"a":[16,67,77,90,102],"system":[17],"interface":[18],"with":[19,41,70],"six":[20],"QuickPath":[21],"interconnect":[25,30],"channels":[26],"memory":[29],"channels.":[31],"The":[32,62],"large":[33],"die":[34],"high":[36],"level":[37],"of":[38,51],"integration":[39],"coupled":[40],"process":[42],"variability":[43,55],"present":[44],"clock-system":[45],"design":[46],"challenges":[47],"in":[48,59],"the":[49,109],"areas":[50],"power":[52],"consumption":[53],"compensation":[56],"that":[57,75,105],"discuss":[58],"this":[60],"paper.":[61],"clock":[63,93],"system,":[64],"which":[65],"is":[66],"cascaded-PLL":[68],"architecture":[69],"an":[71],"initial":[72],"filter":[73],"PLL":[74,84,100],"receives":[76],"133":[78,91],"MHz":[79,92],"reference":[80],"clock.":[81],"This":[82],"maiden":[83],"filters":[85],"reference-clock":[86],"jitter":[87],"outputs":[89],"to":[94],"13":[95],"downstream":[96,99],"PLLs.":[97],"Each":[98],"has":[101],"duty-cycle":[103],"corrector":[104],"monitors":[106],"corrects":[108],"end-of-route":[110],"duty":[111],"cycle.":[112]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":2},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":2},{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
