{"id":"https://openalex.org/W2080418535","doi":"https://doi.org/10.1109/isscc.2009.4977306","title":"A family of 45nm IA processors","display_name":"A family of 45nm IA processors","publication_year":2009,"publication_date":"2009-02-01","ids":{"openalex":"https://openalex.org/W2080418535","doi":"https://doi.org/10.1109/isscc.2009.4977306","mag":"2080418535"},"language":"en","primary_location":{"id":"doi:10.1109/isscc.2009.4977306","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isscc.2009.4977306","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5000147127","display_name":"R. Kumar","orcid":"https://orcid.org/0000-0001-6399-2471"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"R. Kumar","raw_affiliation_strings":["Intel, Hillsboro, OR, USA","[Intel, Hillsboro, OR, USA]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"[Intel, Hillsboro, OR, USA]","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5108093963","display_name":"Geoffrey E. Hinton","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"G. Hinton","raw_affiliation_strings":["Intel, Hillsboro, OR, USA","[Intel, Hillsboro, OR, USA]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"[Intel, Hillsboro, OR, USA]","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I1343180700"],"apc_list":null,"apc_paid":null,"fwci":34.4649,"has_fulltext":false,"cited_by_count":128,"citation_normalized_percentile":{"value":0.99922548,"is_in_top_1_percent":true,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":93,"max":100},"biblio":{"volume":null,"issue":null,"first_page":"58","last_page":"59"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9976000189781189,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/chipset","display_name":"Chipset","score":0.6756657361984253},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.597684919834137},{"id":"https://openalex.org/keywords/coprocessor","display_name":"Coprocessor","score":0.5672472715377808},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5366816520690918},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.4862045645713806},{"id":"https://openalex.org/keywords/cascode","display_name":"Cascode","score":0.4491432309150696},{"id":"https://openalex.org/keywords/modular-design","display_name":"Modular design","score":0.44803425669670105},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.35285764932632446},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.32394981384277344},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.29179394245147705},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.27889424562454224},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.18433263897895813},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.18168747425079346},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.15137049555778503},{"id":"https://openalex.org/keywords/amplifier","display_name":"Amplifier","score":0.13817647099494934}],"concepts":[{"id":"https://openalex.org/C73431340","wikidata":"https://www.wikidata.org/wiki/Q182656","display_name":"Chipset","level":3,"score":0.6756657361984253},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.597684919834137},{"id":"https://openalex.org/C86111242","wikidata":"https://www.wikidata.org/wiki/Q859595","display_name":"Coprocessor","level":2,"score":0.5672472715377808},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5366816520690918},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.4862045645713806},{"id":"https://openalex.org/C2775946640","wikidata":"https://www.wikidata.org/wiki/Q1735017","display_name":"Cascode","level":4,"score":0.4491432309150696},{"id":"https://openalex.org/C101468663","wikidata":"https://www.wikidata.org/wiki/Q1620158","display_name":"Modular design","level":2,"score":0.44803425669670105},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.35285764932632446},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.32394981384277344},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.29179394245147705},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.27889424562454224},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.18433263897895813},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.18168747425079346},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.15137049555778503},{"id":"https://openalex.org/C194257627","wikidata":"https://www.wikidata.org/wiki/Q211554","display_name":"Amplifier","level":3,"score":0.13817647099494934}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isscc.2009.4977306","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isscc.2009.4977306","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.7799999713897705,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W1973152414","https://openalex.org/W2001894083","https://openalex.org/W2092677096","https://openalex.org/W2145173415","https://openalex.org/W2153445207","https://openalex.org/W6650975361"],"related_works":["https://openalex.org/W2361454123","https://openalex.org/W2385247776","https://openalex.org/W2100196563","https://openalex.org/W2127916158","https://openalex.org/W1553497204","https://openalex.org/W2106546050","https://openalex.org/W2382142327","https://openalex.org/W2977359002","https://openalex.org/W2598933208","https://openalex.org/W2093117684"],"abstract_inverted_index":{"Nehalem":[0],"is":[1,56,117],"a":[2,23,47],"family":[3,21],"of":[4],"next-generation":[5],"IA":[6,63],"processors":[7],"for":[8,59,70],"mobile,":[9],"desktop":[10],"and":[11,35,68,80,105,111],"server":[12],"segments":[13],"implemented":[14],"in":[15,32,121],"45nm":[16,94,122],"high-kappa":[17],"metal-gate":[18],"CMOS.":[19],"The":[20,38,93],"features":[22,74,96],"new":[24],"system":[25],"architecture,":[26,30],"significantly":[27],"enhanced":[28],"Core":[29],"innovations":[31],"power":[33,76],"management":[34],"modular":[36],"design.":[37],"4-core":[39],"8MB-L3-cache":[40],"die":[41],"has":[42],"731M":[43],"transistors.":[44],"We":[45],"introduce":[46],"coherent":[48,60],"point-to-":[49],"point":[50],"link":[51],"called":[52],"QuickPath":[53],"Interconnect":[54],"that":[55],"the":[57,84,124],"foundation":[58],"communication":[61],"between":[62],"processors,":[64],"chipsets,":[65],"I/O":[66],"hubs":[67],"coprocessors/accelerators":[69],"multiple":[71],"generations.":[72],"It":[73],"advanced":[75],"management,":[77],"RAS":[78],"capabilities":[79],"reduced":[81],"hops/latency.":[82],"At":[83],"physical":[85],"level,":[86],"it":[87],"uses":[88],"unidirectional":[89],"variable-width":[90],"differential":[91],"signaling.":[92],"implementation":[95],"current-mode":[97],"signaling":[98],"with":[99],"cascode":[100],"driver,":[101],"clock":[102],"forwarding,":[103],"source":[104],"sink":[106],"termination,":[107],"per-bit":[108],"skew":[109],"compensation":[110],"2-tap":[112],"driver":[113],"equalization.":[114],"Signaling":[115],"speed":[116],"up":[118],"to":[119,128],"6.4GT/S":[120],"but":[123],"basic":[125],"approach":[126],"scales":[127],"20GT/s":[129],"using":[130],"conventional":[131],"copper":[132],"interconnect.":[133]},"counts_by_year":[{"year":2022,"cited_by_count":3},{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":3},{"year":2018,"cited_by_count":4},{"year":2017,"cited_by_count":3},{"year":2016,"cited_by_count":3},{"year":2015,"cited_by_count":6},{"year":2014,"cited_by_count":13},{"year":2013,"cited_by_count":18},{"year":2012,"cited_by_count":23}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}
