{"id":"https://openalex.org/W1514031534","doi":"https://doi.org/10.1109/isscc.2008.4523268","title":"A 39.1-to-41.6GHz \u0394\u03a3 Fractional-N Frequency Synthesizer in 90nm CMOS","display_name":"A 39.1-to-41.6GHz \u0394\u03a3 Fractional-N Frequency Synthesizer in 90nm CMOS","publication_year":2008,"publication_date":"2008-02-01","ids":{"openalex":"https://openalex.org/W1514031534","doi":"https://doi.org/10.1109/isscc.2008.4523268","mag":"1514031534"},"language":"en","primary_location":{"id":"doi:10.1109/isscc.2008.4523268","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isscc.2008.4523268","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5065695022","display_name":"Stefano Pellerano","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Stefano Pellerano","raw_affiliation_strings":["Intel, Hillsboro, OR, USA","Intel, Hillsboro OR"],"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel, Hillsboro OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5071379613","display_name":"R. Mukhopadhyay","orcid":"https://orcid.org/0000-0002-0001-0861"},"institutions":[{"id":"https://openalex.org/I74760111","display_name":"Texas Instruments (United States)","ror":"https://ror.org/03vsmv677","country_code":"US","type":"company","lineage":["https://openalex.org/I74760111"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Rajarshi Mukhopadhyay","raw_affiliation_strings":["Texas Instruments, Dallas, TX, USA","Texas Instruments Dallas, TX"],"affiliations":[{"raw_affiliation_string":"Texas Instruments, Dallas, TX, USA","institution_ids":["https://openalex.org/I74760111"]},{"raw_affiliation_string":"Texas Instruments Dallas, TX","institution_ids":["https://openalex.org/I74760111"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5058466731","display_name":"Ashoke Ravi","orcid":"https://orcid.org/0000-0001-8302-622X"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ashoke Ravi","raw_affiliation_strings":["Intel, Hillsboro, OR, USA","Intel, Hillsboro OR"],"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel, Hillsboro OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111452226","display_name":"Joy Laskar","orcid":null},"institutions":[{"id":"https://openalex.org/I130701444","display_name":"Georgia Institute of Technology","ror":"https://ror.org/01zkghx44","country_code":"US","type":"education","lineage":["https://openalex.org/I130701444"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Joy Laskar","raw_affiliation_strings":["Georgia Institute of Technology, Atlanta, GA, USA","Georgia Institute of Technology Atlanta, GA"],"affiliations":[{"raw_affiliation_string":"Georgia Institute of Technology, Atlanta, GA, USA","institution_ids":["https://openalex.org/I130701444"]},{"raw_affiliation_string":"Georgia Institute of Technology Atlanta, GA","institution_ids":["https://openalex.org/I130701444"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5079858274","display_name":"Yorgos Palaskas","orcid":"https://orcid.org/0000-0003-0551-7327"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Yorgos Palaskas","raw_affiliation_strings":["Intel, Hillsboro, OR, USA","Intel, Hillsboro OR"],"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel, Hillsboro OR","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5065695022"],"corresponding_institution_ids":["https://openalex.org/I1343180700"],"apc_list":null,"apc_paid":null,"fwci":4.6612,"has_fulltext":false,"cited_by_count":39,"citation_normalized_percentile":{"value":0.94500378,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"484","last_page":"630"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9979000091552734,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.8458125591278076},{"id":"https://openalex.org/keywords/frequency-divider","display_name":"Frequency divider","score":0.7865836024284363},{"id":"https://openalex.org/keywords/frequency-synthesizer","display_name":"Frequency synthesizer","score":0.763312578201294},{"id":"https://openalex.org/keywords/direct-digital-synthesizer","display_name":"Direct digital synthesizer","score":0.5984820127487183},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5851409435272217},{"id":"https://openalex.org/keywords/power-consumption","display_name":"Power consumption","score":0.559386670589447},{"id":"https://openalex.org/keywords/calibration","display_name":"Calibration","score":0.5023694038391113},{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.482326477766037},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.41366058588027954},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.4095616340637207},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.3685588240623474},{"id":"https://openalex.org/keywords/phase-noise","display_name":"Phase noise","score":0.29227131605148315},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.24558770656585693},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.15136975049972534}],"concepts":[{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.8458125591278076},{"id":"https://openalex.org/C74982907","wikidata":"https://www.wikidata.org/wiki/Q1455624","display_name":"Frequency divider","level":3,"score":0.7865836024284363},{"id":"https://openalex.org/C182099602","wikidata":"https://www.wikidata.org/wiki/Q2660678","display_name":"Frequency synthesizer","level":4,"score":0.763312578201294},{"id":"https://openalex.org/C166089067","wikidata":"https://www.wikidata.org/wiki/Q1227465","display_name":"Direct digital synthesizer","level":5,"score":0.5984820127487183},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5851409435272217},{"id":"https://openalex.org/C2984118289","wikidata":"https://www.wikidata.org/wiki/Q29954","display_name":"Power consumption","level":3,"score":0.559386670589447},{"id":"https://openalex.org/C165838908","wikidata":"https://www.wikidata.org/wiki/Q736777","display_name":"Calibration","level":2,"score":0.5023694038391113},{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.482326477766037},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.41366058588027954},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.4095616340637207},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.3685588240623474},{"id":"https://openalex.org/C89631360","wikidata":"https://www.wikidata.org/wiki/Q1428766","display_name":"Phase noise","level":2,"score":0.29227131605148315},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.24558770656585693},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.15136975049972534},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isscc.2008.4523268","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isscc.2008.4523268","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.8999999761581421}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W1963721450","https://openalex.org/W2010817526","https://openalex.org/W2030451389","https://openalex.org/W2046968876","https://openalex.org/W2075316336","https://openalex.org/W2154282288","https://openalex.org/W2171663093"],"related_works":["https://openalex.org/W3145870900","https://openalex.org/W2350523680","https://openalex.org/W2353586717","https://openalex.org/W2371350995","https://openalex.org/W2379961307","https://openalex.org/W2376421545","https://openalex.org/W2110035284","https://openalex.org/W2374761771","https://openalex.org/W2354027044","https://openalex.org/W2359366503"],"abstract_inverted_index":{"In":[0],"this":[1],"paper,":[2],"we":[3],"present":[4],"a":[5,26,39],"39.1-to-41.6":[6],"GHz":[7],"1.2":[8],"V":[9],"64":[10],"mW":[11],"DeltaSigma":[12],"fractional-N":[13],"frequency":[14,29],"synthesizer":[15],"that":[16],"is":[17,32,43],"implemented":[18,44],"in":[19,34],"90nm":[20],"CMOS.":[21],"To":[22],"reduce":[23],"power":[24],"consumption,":[25],"divide-by-4":[27],"injection-locking":[28],"divider":[30],"(ILFD)":[31],"used":[33],"the":[35,47],"feedback":[36],"loop":[37],"and":[38],"digital":[40],"calibration":[41],"technique":[42],"to":[45],"overcome":[46],"ILFD":[48],"locking-range":[49],"limitations.":[50]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":2},{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":3},{"year":2015,"cited_by_count":5},{"year":2014,"cited_by_count":5},{"year":2012,"cited_by_count":5}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
