{"id":"https://openalex.org/W1986236050","doi":"https://doi.org/10.1109/isscc.2008.4523154","title":"A Sub-1W to 2W Low-Power IA Processor for Mobile Internet Devices and Ultra-Mobile PCs in 45nm Hi-\u00bf Metal Gate CMOS","display_name":"A Sub-1W to 2W Low-Power IA Processor for Mobile Internet Devices and Ultra-Mobile PCs in 45nm Hi-\u00bf Metal Gate CMOS","publication_year":2008,"publication_date":"2008-02-01","ids":{"openalex":"https://openalex.org/W1986236050","doi":"https://doi.org/10.1109/isscc.2008.4523154","mag":"1986236050"},"language":"en","primary_location":{"id":"doi:10.1109/isscc.2008.4523154","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isscc.2008.4523154","pdf_url":null,"source":{"id":"https://openalex.org/S4210210374","display_name":"Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference","issn_l":"0193-6530","issn":["0193-6530","2376-8606"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5113448461","display_name":"Gianfranco Gerosa","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Gianfranco Gerosa","raw_affiliation_strings":["Intel, Austin, TX, USA","Intel, Austin, TX"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel, Austin, TX, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel, Austin, TX","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111573811","display_name":"Steve Curtis","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Steve Curtis","raw_affiliation_strings":["Intel, Austin, TX, USA","Intel, Austin, TX"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel, Austin, TX, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel, Austin, TX","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5035178513","display_name":"M. D'Addeo","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Mike D'Addeo","raw_affiliation_strings":["Intel, Austin, TX"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel, Austin, TX","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100608481","display_name":"Bo Jiang","orcid":"https://orcid.org/0000-0002-3272-958X"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Bo Jiang","raw_affiliation_strings":["Intel, Austin, TX, USA","Intel, Austin, TX"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel, Austin, TX, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel, Austin, TX","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5110082481","display_name":"Belliappa Kuttanna","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Belliappa Kuttanna","raw_affiliation_strings":["Intel, Austin, TX, USA","Intel, Austin, TX"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel, Austin, TX, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel, Austin, TX","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5080731156","display_name":"Feroze Merchant","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Feroze Merchant","raw_affiliation_strings":["Intel, Austin, TX, USA","Intel, Austin, TX"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel, Austin, TX, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel, Austin, TX","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5001084136","display_name":"Binta Patel","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Binta Patel","raw_affiliation_strings":["Intel, Austin, TX, USA","Intel, Austin, TX"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel, Austin, TX, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel, Austin, TX","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5038721597","display_name":"Mohammed Taufique","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Mohammed Taufique","raw_affiliation_strings":["Intel, Austin, TX, USA","Intel, Austin, TX"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel, Austin, TX, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel, Austin, TX","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5003699549","display_name":"Haytham Samarchi","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Haytham Samarchi","raw_affiliation_strings":["Intel, Austin, TX, USA","Intel, Austin, TX"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel, Austin, TX, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel, Austin, TX","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":9,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":10.5144,"has_fulltext":false,"cited_by_count":54,"citation_normalized_percentile":{"value":0.98553808,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":90,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"256","last_page":"611"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9927999973297119,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6440775394439697},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.47375068068504333},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4171207547187805},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.3865908980369568},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.25422751903533936}],"concepts":[{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6440775394439697},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.47375068068504333},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4171207547187805},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.3865908980369568},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.25422751903533936}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isscc.2008.4523154","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isscc.2008.4523154","pdf_url":null,"source":{"id":"https://openalex.org/S4210210374","display_name":"Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference","issn_l":"0193-6530","issn":["0193-6530","2376-8606"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.8100000023841858}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W2001894083","https://openalex.org/W2096046678","https://openalex.org/W2126898248","https://openalex.org/W2540193588","https://openalex.org/W6650975361"],"related_works":["https://openalex.org/W2748952813","https://openalex.org/W3014521742","https://openalex.org/W2390279801","https://openalex.org/W2358668433","https://openalex.org/W2617868873","https://openalex.org/W3204141294","https://openalex.org/W2376932109","https://openalex.org/W2001405890","https://openalex.org/W4386230336","https://openalex.org/W4306968100"],"abstract_inverted_index":{"This":[0],"paper":[1],"describes":[2],"a":[3,30,86,91,107,118,131,152,157],"low-power":[4],"Intel*":[5],"Architecture":[6],"(IA)":[7],"processor":[8],"specifically":[9],"designed":[10],"for":[11,126],"Mobile":[12,18],"Internet":[13],"Devices":[14],"(MID)":[15],"and":[16,69,76,90,96],"Ultra-":[17],"PCs":[19],"(UMPC)":[20],"where":[21],"average":[22],"power":[23],"consumed":[24],"is":[25,146],"in":[26,106,117,130],"the":[27],"order":[28],"of":[29,53,58,159],"few":[31],"hundred":[32],"mW":[33],"(as":[34],"measured":[35,147],"by":[36],"MobileMark'05":[37],"OP":[38],"@":[39],"60":[40],"nits":[41],"brightness)":[42],"with":[43,123],"performance":[44],"similar":[45],"to":[46],"mainstream":[47],"Ultra-Mobile":[48],"PCs.":[49],"The":[50,100],"design":[51,101],"consists":[52],"an":[54],"in-order":[55],"pipeline":[56],"capable":[57],"issuing":[59],"2":[60,65,149,160],"instructions":[61],"per":[62],"cycle":[63],"supporting":[64],"threads,":[66],"32KB":[67],"instruction":[68],"24KB":[70],"data":[71],"LI":[72],"caches,":[73],"independent":[74],"integer":[75],"floating":[77],"point":[78],"execution":[79,84],"units,":[80],"x86":[81],"front":[82],"end":[83],"unit,":[85],"512KB":[87],"L2":[88],"cache":[89],"533":[92],"MT/s":[93],"dual-mode":[94],"(GTL":[95],"CMOS)":[97],"front-side-bus":[98],"(FSB).":[99],"contains":[102],"47":[103],"M":[104],"transistors":[105,125],"die":[108],"size":[109],"under":[110],"25":[111],"mm":[112,136],"<sup":[113,137],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[114,138],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">2</sup>":[115,139],"manufactured":[116],"9-metal":[119],"45nm":[120],"CMOS":[121],"process":[122],"optimized":[124],"low":[127],"leakage":[128],"packaged":[129],"Halide-Free":[132],"441":[133],"ball,":[134],"14x13":[135],"muFCBGA.":[140],"Thermal":[141],"Design":[142],"Power":[143],"(TDP)":[144],"consumption":[145],"at":[148,156],"W":[150],"using":[151],"synthetic":[153],"power-virus":[154],"test":[155],"frequency":[158],"GHz.":[161]},"counts_by_year":[{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":2},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":10},{"year":2012,"cited_by_count":5}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}