{"id":"https://openalex.org/W1968024299","doi":"https://doi.org/10.1109/isscc.2008.4523061","title":"A Continuous-Time Hexagonal Field-Programmable Analog Array in 0.13\u03bcm CMOS with 186MHz GBW","display_name":"A Continuous-Time Hexagonal Field-Programmable Analog Array in 0.13\u03bcm CMOS with 186MHz GBW","publication_year":2008,"publication_date":"2008-02-01","ids":{"openalex":"https://openalex.org/W1968024299","doi":"https://doi.org/10.1109/isscc.2008.4523061","mag":"1968024299"},"language":"en","primary_location":{"id":"doi:10.1109/isscc.2008.4523061","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isscc.2008.4523061","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5067122803","display_name":"Joachim Becker","orcid":"https://orcid.org/0000-0002-2125-7812"},"institutions":[{"id":"https://openalex.org/I161046081","display_name":"University of Freiburg","ror":"https://ror.org/0245cg223","country_code":"DE","type":"education","lineage":["https://openalex.org/I161046081"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"J. Becker","raw_affiliation_strings":["University of Freiburg, IMTEK, Freiburg im Breisgau, Germany","IMTEK, Univ. of Freiburg, Freiburg"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Freiburg, IMTEK, Freiburg im Breisgau, Germany","institution_ids":["https://openalex.org/I161046081"]},{"raw_affiliation_string":"IMTEK, Univ. of Freiburg, Freiburg","institution_ids":["https://openalex.org/I161046081"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5007884064","display_name":"Fabian Henrici","orcid":null},"institutions":[{"id":"https://openalex.org/I161046081","display_name":"University of Freiburg","ror":"https://ror.org/0245cg223","country_code":"DE","type":"education","lineage":["https://openalex.org/I161046081"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"F. Henrici","raw_affiliation_strings":["University of Freiburg, IMTEK, Freiburg im Breisgau, Germany","IMTEK, Univ. of Freiburg, Freiburg"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Freiburg, IMTEK, Freiburg im Breisgau, Germany","institution_ids":["https://openalex.org/I161046081"]},{"raw_affiliation_string":"IMTEK, Univ. of Freiburg, Freiburg","institution_ids":["https://openalex.org/I161046081"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5079818503","display_name":"Stanis Trendelenburg","orcid":null},"institutions":[{"id":"https://openalex.org/I161046081","display_name":"University of Freiburg","ror":"https://ror.org/0245cg223","country_code":"DE","type":"education","lineage":["https://openalex.org/I161046081"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"S. Trendelenburg","raw_affiliation_strings":["University of Freiburg, IMTEK, Freiburg im Breisgau, Germany","IMTEK, Univ. of Freiburg, Freiburg"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Freiburg, IMTEK, Freiburg im Breisgau, Germany","institution_ids":["https://openalex.org/I161046081"]},{"raw_affiliation_string":"IMTEK, Univ. of Freiburg, Freiburg","institution_ids":["https://openalex.org/I161046081"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5034938079","display_name":"Maurits Ortmanns","orcid":"https://orcid.org/0000-0002-3547-1596"},"institutions":[{"id":"https://openalex.org/I161046081","display_name":"University of Freiburg","ror":"https://ror.org/0245cg223","country_code":"DE","type":"education","lineage":["https://openalex.org/I161046081"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"M. Ortmanns","raw_affiliation_strings":["University of Freiburg, IMTEK, Freiburg im Breisgau, Germany","IMTEK, Univ. of Freiburg, Freiburg"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Freiburg, IMTEK, Freiburg im Breisgau, Germany","institution_ids":["https://openalex.org/I161046081"]},{"raw_affiliation_string":"IMTEK, Univ. of Freiburg, Freiburg","institution_ids":["https://openalex.org/I161046081"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5052080512","display_name":"Yiannos Manoli","orcid":"https://orcid.org/0000-0003-2805-0539"},"institutions":[{"id":"https://openalex.org/I161046081","display_name":"University of Freiburg","ror":"https://ror.org/0245cg223","country_code":"DE","type":"education","lineage":["https://openalex.org/I161046081"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Y. Manoli","raw_affiliation_strings":["University of Freiburg, IMTEK, Freiburg im Breisgau, Germany","IMTEK, Univ. of Freiburg, Freiburg"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Freiburg, IMTEK, Freiburg im Breisgau, Germany","institution_ids":["https://openalex.org/I161046081"]},{"raw_affiliation_string":"IMTEK, Univ. of Freiburg, Freiburg","institution_ids":["https://openalex.org/I161046081"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I161046081"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":24,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"70","last_page":"596"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-analog-array","display_name":"Field-programmable analog array","score":0.8131847977638245},{"id":"https://openalex.org/keywords/microelectronics","display_name":"Microelectronics","score":0.6957287788391113},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6862474679946899},{"id":"https://openalex.org/keywords/analogue-electronics","display_name":"Analogue electronics","score":0.6618223190307617},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6190829277038574},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5946092009544373},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.5809618234634399},{"id":"https://openalex.org/keywords/field","display_name":"Field (mathematics)","score":0.5403521060943604},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.5268161296844482},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.5112104415893555},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.4900604486465454},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.4838480055332184},{"id":"https://openalex.org/keywords/programmable-array-logic","display_name":"Programmable Array Logic","score":0.4608156085014343},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.44974640011787415},{"id":"https://openalex.org/keywords/programmable-logic-array","display_name":"Programmable logic array","score":0.44088485836982727},{"id":"https://openalex.org/keywords/mixed-signal-integrated-circuit","display_name":"Mixed-signal integrated circuit","score":0.4396900236606598},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.4197801351547241},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.3957456648349762},{"id":"https://openalex.org/keywords/analog-multiplier","display_name":"Analog multiplier","score":0.3674917221069336},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.32950928807258606},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.30396702885627747},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2880687117576599},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2820378243923187},{"id":"https://openalex.org/keywords/analog-signal","display_name":"Analog signal","score":0.23633238673210144},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.08232429623603821},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.07766878604888916}],"concepts":[{"id":"https://openalex.org/C149128552","wikidata":"https://www.wikidata.org/wiki/Q380201","display_name":"Field-programmable analog array","level":5,"score":0.8131847977638245},{"id":"https://openalex.org/C187937830","wikidata":"https://www.wikidata.org/wiki/Q175403","display_name":"Microelectronics","level":2,"score":0.6957287788391113},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6862474679946899},{"id":"https://openalex.org/C29074008","wikidata":"https://www.wikidata.org/wiki/Q174925","display_name":"Analogue electronics","level":3,"score":0.6618223190307617},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6190829277038574},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5946092009544373},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.5809618234634399},{"id":"https://openalex.org/C9652623","wikidata":"https://www.wikidata.org/wiki/Q190109","display_name":"Field (mathematics)","level":2,"score":0.5403521060943604},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.5268161296844482},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5112104415893555},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.4900604486465454},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.4838480055332184},{"id":"https://openalex.org/C113323844","wikidata":"https://www.wikidata.org/wiki/Q1378651","display_name":"Programmable Array Logic","level":5,"score":0.4608156085014343},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.44974640011787415},{"id":"https://openalex.org/C182322920","wikidata":"https://www.wikidata.org/wiki/Q2112217","display_name":"Programmable logic array","level":3,"score":0.44088485836982727},{"id":"https://openalex.org/C62907940","wikidata":"https://www.wikidata.org/wiki/Q1541329","display_name":"Mixed-signal integrated circuit","level":3,"score":0.4396900236606598},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.4197801351547241},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.3957456648349762},{"id":"https://openalex.org/C98142538","wikidata":"https://www.wikidata.org/wiki/Q485005","display_name":"Analog multiplier","level":4,"score":0.3674917221069336},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.32950928807258606},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.30396702885627747},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2880687117576599},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2820378243923187},{"id":"https://openalex.org/C13412647","wikidata":"https://www.wikidata.org/wiki/Q174948","display_name":"Analog signal","level":3,"score":0.23633238673210144},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.08232429623603821},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.07766878604888916},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C202444582","wikidata":"https://www.wikidata.org/wiki/Q837863","display_name":"Pure mathematics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isscc.2008.4523061","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isscc.2008.4523061","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":3,"referenced_works":["https://openalex.org/W2038078811","https://openalex.org/W2141566055","https://openalex.org/W2145183934"],"related_works":["https://openalex.org/W2100931776","https://openalex.org/W4250289642","https://openalex.org/W2148121214","https://openalex.org/W2008534674","https://openalex.org/W4229794591","https://openalex.org/W2091126337","https://openalex.org/W2133813997","https://openalex.org/W1968024299","https://openalex.org/W2162081665","https://openalex.org/W1493881961"],"abstract_inverted_index":{"The":[0],"high":[1],"non-recurring":[2],"engineering":[3],"costs":[4],"of":[5,14,38,52,61],"integrated":[6],"circuit":[7],"design":[8],"make":[9],"rapid-prototyping":[10],"an":[11],"important":[12],"field":[13],"microelectronics.":[15],"For":[16],"digital":[17],"circuits,":[18],"FPGAs":[19],"are":[20,72],"highly":[21],"developed":[22],"and":[23,31,45,64,79],"have":[24,80],"become":[25],"indispensable":[26],"as":[27],"both":[28],"development":[29],"tools":[30],"application":[32,78],"platforms.":[33],"In":[34],"contrast,":[35],"the":[36,76],"nature":[37],"analog":[39,55,69],"circuits":[40],"is":[41],"much":[42],"more":[43],"complex":[44],"does":[46],"not":[47],"readily":[48],"allow":[49],"a":[50,58],"mapping":[51],"any":[53],"arbitrary":[54],"behavior":[56],"to":[57,75,85],"generic":[59],"set":[60],"basic":[62],"building-blocks":[63],"routing":[65],"nodes.":[66],"Therefore,":[67],"field-programmable":[68],"arrays":[70],"(FPAAs)":[71],"very":[73],"specific":[74],"target":[77],"poor":[81],"performance":[82],"when":[83],"compared":[84],"single-purpose":[86],"ASICs.":[87]},"counts_by_year":[{"year":2022,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":2},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":2},{"year":2012,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}
