{"id":"https://openalex.org/W1988359544","doi":"https://doi.org/10.1109/isscc.2006.1696304","title":"A PVT-Tolerant Low-1/f Noise Dual-Loop Hybrid PLL in 0.18/spl mu/m","display_name":"A PVT-Tolerant Low-1/f Noise Dual-Loop Hybrid PLL in 0.18/spl mu/m","publication_year":2006,"publication_date":"2006-01-01","ids":{"openalex":"https://openalex.org/W1988359544","doi":"https://doi.org/10.1109/isscc.2006.1696304","mag":"1988359544"},"language":"en","primary_location":{"id":"doi:10.1109/isscc.2006.1696304","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isscc.2006.1696304","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5077521123","display_name":"Hyung-Rok Lee","orcid":null},"institutions":[{"id":"https://openalex.org/I139264467","display_name":"Seoul National University","ror":"https://ror.org/04h9pn542","country_code":"KR","type":"education","lineage":["https://openalex.org/I139264467"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Hyung-Rok Lee","raw_affiliation_strings":["Seoul National University, Seoul, South Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Seoul National University, Seoul, South Korea","institution_ids":["https://openalex.org/I139264467"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5077762904","display_name":"Ook Kim","orcid":null},"institutions":[{"id":"https://openalex.org/I93085520","display_name":"Silicon Labs (United States)","ror":"https://ror.org/02dyqfb80","country_code":"US","type":"company","lineage":["https://openalex.org/I93085520"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ook Kim","raw_affiliation_strings":["Silicon Image, Inc., Sunnyvale, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Silicon Image, Inc., Sunnyvale, CA, USA","institution_ids":["https://openalex.org/I93085520"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5113512900","display_name":"Keewook Jung","orcid":null},"institutions":[{"id":"https://openalex.org/I93085520","display_name":"Silicon Labs (United States)","ror":"https://ror.org/02dyqfb80","country_code":"US","type":"company","lineage":["https://openalex.org/I93085520"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Keewook Jung","raw_affiliation_strings":["Silicon Image, Inc., Sunnyvale, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Silicon Image, Inc., Sunnyvale, CA, USA","institution_ids":["https://openalex.org/I93085520"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5113656443","display_name":"J. Shin","orcid":"https://orcid.org/0009-0000-2873-4856"},"institutions":[{"id":"https://openalex.org/I93085520","display_name":"Silicon Labs (United States)","ror":"https://ror.org/02dyqfb80","country_code":"US","type":"company","lineage":["https://openalex.org/I93085520"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"J. Shin","raw_affiliation_strings":["Silicon Image, Inc., Sunnyvale, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Silicon Image, Inc., Sunnyvale, CA, USA","institution_ids":["https://openalex.org/I93085520"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5008010401","display_name":"Deog\u2010Kyoon Jeong","orcid":"https://orcid.org/0000-0003-0436-703X"},"institutions":[{"id":"https://openalex.org/I139264467","display_name":"Seoul National University","ror":"https://ror.org/04h9pn542","country_code":"KR","type":"education","lineage":["https://openalex.org/I139264467"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Deog-Kyoon Jeong","raw_affiliation_strings":["Seoul National University, Seoul, South Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Seoul National University, Seoul, South Korea","institution_ids":["https://openalex.org/I139264467"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":5,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.3834,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.63652392,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"2402","last_page":"2411"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9980999827384949,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9954000115394592,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.8730815649032593},{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.7912834882736206},{"id":"https://openalex.org/keywords/bandwidth","display_name":"Bandwidth (computing)","score":0.6610360145568848},{"id":"https://openalex.org/keywords/dual-loop","display_name":"Dual loop","score":0.6471772193908691},{"id":"https://openalex.org/keywords/voltage-controlled-oscillator","display_name":"Voltage-controlled oscillator","score":0.5471394062042236},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.546436071395874},{"id":"https://openalex.org/keywords/loop","display_name":"Loop (graph theory)","score":0.5424739122390747},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5315169095993042},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5127654671669006},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.4726128876209259},{"id":"https://openalex.org/keywords/phase-noise","display_name":"Phase noise","score":0.44894999265670776},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.33692461252212524},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.24964389204978943},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.1223730742931366},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.09939393401145935}],"concepts":[{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.8730815649032593},{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.7912834882736206},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.6610360145568848},{"id":"https://openalex.org/C2779691726","wikidata":"https://www.wikidata.org/wiki/Q5310214","display_name":"Dual loop","level":3,"score":0.6471772193908691},{"id":"https://openalex.org/C5291336","wikidata":"https://www.wikidata.org/wiki/Q852341","display_name":"Voltage-controlled oscillator","level":3,"score":0.5471394062042236},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.546436071395874},{"id":"https://openalex.org/C184670325","wikidata":"https://www.wikidata.org/wiki/Q512604","display_name":"Loop (graph theory)","level":2,"score":0.5424739122390747},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5315169095993042},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5127654671669006},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4726128876209259},{"id":"https://openalex.org/C89631360","wikidata":"https://www.wikidata.org/wiki/Q1428766","display_name":"Phase noise","level":2,"score":0.44894999265670776},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.33692461252212524},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.24964389204978943},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.1223730742931366},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.09939393401145935},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.0},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isscc.2006.1696304","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isscc.2006.1696304","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.6800000071525574}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":3,"referenced_works":["https://openalex.org/W1558242838","https://openalex.org/W2102168960","https://openalex.org/W2120258930"],"related_works":["https://openalex.org/W2976219355","https://openalex.org/W1994021281","https://openalex.org/W3129408886","https://openalex.org/W4233090067","https://openalex.org/W2365946217","https://openalex.org/W1964543336","https://openalex.org/W2139484866","https://openalex.org/W2368638770","https://openalex.org/W2365449259","https://openalex.org/W2089131288"],"abstract_inverted_index":{"A":[0],"dual-loop":[1],"analog-digital":[2],"hybrid":[3],"PLL":[4],"with":[5],"a":[6,33,58,66],"small-bandwidth":[7],"digital":[8],"loop":[9,13,26],"and":[10,21,62],"large-bandwidth":[11],"analog":[12],"achieves":[14],"low":[15],"jitter":[16,43],"by":[17],"suppressing":[18],"1/f":[19],"noise":[20],"does":[22],"not":[23],"require":[24],"off-chip":[25],"filter":[27],"components.":[28],"The":[29,41,53],"operating":[30],"range":[31,46],"using":[32],"narrow-range":[34],"VCO":[35],"is":[36,47,55],"from":[37,65],"10":[38],"to":[39],"200MHz.":[40],"output":[42],"over":[44],"this":[45],"<0.028UI":[48],"<sub":[49],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[50],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">pp</sub>":[51],".":[52],"chip":[54],"implemented":[56],"in":[57],"0.18mum":[59],"CMOS":[60],"process":[61],"consumes":[63],"50mW":[64],"1.8V":[67],"supply":[68]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2015,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
