{"id":"https://openalex.org/W2051743745","doi":"https://doi.org/10.1109/isscc.2006.1696235","title":"An 8.8GHz 198mW 16x64b 1R/1W variationtolerant register file in 65nm CMOS","display_name":"An 8.8GHz 198mW 16x64b 1R/1W variationtolerant register file in 65nm CMOS","publication_year":2006,"publication_date":"2006-01-01","ids":{"openalex":"https://openalex.org/W2051743745","doi":"https://doi.org/10.1109/isscc.2006.1696235","mag":"2051743745"},"language":"en","primary_location":{"id":"doi:10.1109/isscc.2006.1696235","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isscc.2006.1696235","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5109340111","display_name":"Steven Hsu","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"S. Hsu","raw_affiliation_strings":["Intel, Hillsboro, OR, USA","Intel, Hillsboro OR"],"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel, Hillsboro OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5006348328","display_name":"Amit Agarwal","orcid":"https://orcid.org/0000-0002-4220-3346"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"A. Agarwal","raw_affiliation_strings":["Intel, Hillsboro, OR, USA","Intel, Hillsboro OR"],"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel, Hillsboro OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5052106795","display_name":"Mark Anders","orcid":"https://orcid.org/0000-0001-5748-8420"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"M. Anders","raw_affiliation_strings":["Intel, Hillsboro, OR, USA","Intel, Hillsboro OR"],"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel, Hillsboro OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5039276616","display_name":"Sanu Mathew","orcid":"https://orcid.org/0000-0003-1344-7533"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"S. Mathew","raw_affiliation_strings":["Intel, Hillsboro, OR, USA","Intel, Hillsboro OR"],"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel, Hillsboro OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5074107306","display_name":"Ram Krishnamurthy","orcid":"https://orcid.org/0000-0002-2428-7099"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"R. Krishnamurthy","raw_affiliation_strings":["Intel, Hillsboro, OR, USA","Intel, Hillsboro OR"],"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel, Hillsboro OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5112875487","display_name":"Shekhar Borkar","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"S. Borkar","raw_affiliation_strings":["Intel, Hillsboro, OR, USA","Intel, Hillsboro OR"],"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel, Hillsboro OR","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5109340111"],"corresponding_institution_ids":["https://openalex.org/I1343180700"],"apc_list":null,"apc_paid":null,"fwci":1.5044,"has_fulltext":false,"cited_by_count":10,"citation_normalized_percentile":{"value":0.82714021,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"1785","last_page":"1797"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.8020939230918884},{"id":"https://openalex.org/keywords/register-file","display_name":"Register file","score":0.7976043820381165},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6107156276702881},{"id":"https://openalex.org/keywords/leakage","display_name":"Leakage (economics)","score":0.5727750658988953},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.5617055892944336},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.5148128867149353},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.366424560546875},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2411133348941803},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2249690294265747},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.21012073755264282},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.19019919633865356},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.1590651571750641}],"concepts":[{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.8020939230918884},{"id":"https://openalex.org/C117280010","wikidata":"https://www.wikidata.org/wiki/Q180944","display_name":"Register file","level":3,"score":0.7976043820381165},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6107156276702881},{"id":"https://openalex.org/C2777042071","wikidata":"https://www.wikidata.org/wiki/Q6509304","display_name":"Leakage (economics)","level":2,"score":0.5727750658988953},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.5617055892944336},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.5148128867149353},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.366424560546875},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2411133348941803},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2249690294265747},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.21012073755264282},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.19019919633865356},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.1590651571750641},{"id":"https://openalex.org/C139719470","wikidata":"https://www.wikidata.org/wiki/Q39680","display_name":"Macroeconomics","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isscc.2006.1696235","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isscc.2006.1696235","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.6600000262260437}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W1550639219","https://openalex.org/W1570153707","https://openalex.org/W1597266114","https://openalex.org/W1933906492","https://openalex.org/W6634152223"],"related_works":["https://openalex.org/W2042399072","https://openalex.org/W2356166161","https://openalex.org/W3144620029","https://openalex.org/W4249089198","https://openalex.org/W2130533867","https://openalex.org/W2540018280","https://openalex.org/W2139082473","https://openalex.org/W2045163867","https://openalex.org/W2059502833","https://openalex.org/W2155131180"],"abstract_inverted_index":{"A":[0],"16X64b":[1],"1R/1W":[2],"register":[3],"file":[4],"is":[5],"fabricated":[6],"in":[7,24],"65nm":[8],"CMOS":[9],"technology.":[10],"The":[11],"0.017mm":[12],"<sup":[13],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[14],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">2</sup>":[15],"chip":[16],"performs":[17],"8.8GHz":[18],"fused":[19],"decode":[20],"and":[21,48,64],"read/write":[22],"operations":[23],"a":[25,65],"single":[26],"cycle":[27],"while":[28],"dissipating":[29],"198mW":[30],"at":[31,39],"1.2V,":[32],"50\u00b0C,":[33],"with":[34,58],"frequency":[35],"scalable":[36],"to":[37],"10.1GHz":[38],"1.4V,":[40],"50degC.":[41],"Variation-tolerant":[42],"keeper":[43],"compensation,":[44],"leakage-tolerant":[45],"BL/WL":[46],"architecture":[47],"optimal":[49],"non-minimum":[50],"channel-length":[51],"usage":[52],"enable":[53],"wide":[54],"PVT":[55],"operating":[56],"range":[57],"an":[59],"active":[60],"leakage":[61],"of":[62],"25mW":[63],"BL":[66],"noise":[67],"droop":[68],"les8mV":[69]},"counts_by_year":[{"year":2019,"cited_by_count":2},{"year":2016,"cited_by_count":1},{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
