{"id":"https://openalex.org/W2126585617","doi":"https://doi.org/10.1109/isscc.2006.1696129","title":"A monolithic low-bandwidth jitter-cleaning PLL with hitless switching for SONET/SDH clock generation","display_name":"A monolithic low-bandwidth jitter-cleaning PLL with hitless switching for SONET/SDH clock generation","publication_year":2006,"publication_date":"2006-01-01","ids":{"openalex":"https://openalex.org/W2126585617","doi":"https://doi.org/10.1109/isscc.2006.1696129","mag":"2126585617"},"language":"en","primary_location":{"id":"doi:10.1109/isscc.2006.1696129","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isscc.2006.1696129","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5073388655","display_name":"D.C. Wei","orcid":null},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"D.C. Wei","raw_affiliation_strings":["Sillcon Laboratories, Austin, TX"],"affiliations":[{"raw_affiliation_string":"Sillcon Laboratories, Austin, TX","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5091292622","display_name":"Yunteng Huang","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Yunteng Huang","raw_affiliation_strings":["Sillcon Laboratories, Austin, TX"],"affiliations":[{"raw_affiliation_string":"Sillcon Laboratories, Austin, TX","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5053176495","display_name":"B.W. Garlepp","orcid":null},"institutions":[{"id":"https://openalex.org/I4210095722","display_name":"Rambus (United States)","ror":"https://ror.org/00pn5a327","country_code":"US","type":"company","lineage":["https://openalex.org/I4210095722"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"B.W. Garlepp","raw_affiliation_strings":["Rambus, Los Altos, CA"],"affiliations":[{"raw_affiliation_string":"Rambus, Los Altos, CA","institution_ids":["https://openalex.org/I4210095722"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5017493033","display_name":"J.P. Hein","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"J. Hein","raw_affiliation_strings":["Sillcon Laboratories, Austin, TX"],"affiliations":[{"raw_affiliation_string":"Sillcon Laboratories, Austin, TX","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5073388655"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.1283,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":{"value":0.80159344,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":"36","issue":null,"first_page":"884","last_page":"893"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11429","display_name":"Semiconductor Lasers and Optical Devices","score":0.9977999925613403,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.9188065528869629},{"id":"https://openalex.org/keywords/synchronous-optical-networking","display_name":"Synchronous optical networking","score":0.9102955460548401},{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.7485684752464294},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.5961693525314331},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5479916334152222},{"id":"https://openalex.org/keywords/bandwidth","display_name":"Bandwidth (computing)","score":0.4847642779350281},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.46406254172325134},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.45830750465393066},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.23922070860862732},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.17946553230285645}],"concepts":[{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.9188065528869629},{"id":"https://openalex.org/C198306430","wikidata":"https://www.wikidata.org/wiki/Q51823","display_name":"Synchronous optical networking","level":2,"score":0.9102955460548401},{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.7485684752464294},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.5961693525314331},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5479916334152222},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.4847642779350281},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.46406254172325134},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.45830750465393066},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.23922070860862732},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.17946553230285645}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isscc.2006.1696129","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isscc.2006.1696129","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.46000000834465027,"display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":2,"referenced_works":["https://openalex.org/W1752262138","https://openalex.org/W2149785845"],"related_works":["https://openalex.org/W2488704204","https://openalex.org/W2319112762","https://openalex.org/W2018018876","https://openalex.org/W2146180687","https://openalex.org/W2293780457","https://openalex.org/W2121182846","https://openalex.org/W2089248963","https://openalex.org/W2139484866","https://openalex.org/W2787167665","https://openalex.org/W2141230116"],"abstract_inverted_index":{"A":[0],"single-chip":[1],"jitter-cleaning":[2],"PLL":[3],"with":[4],"hitless":[5],"switching":[6,22],"is":[7,23,39,44,61],"presented.":[8],"By":[9],"utilizing":[10],"the":[11,16,28,33,47],"mostly-digital":[12],"phase":[13,19,36],"build-out":[14],"technique,":[15],"steady-state":[17],"output":[18,35],"step":[20],"after":[21],"bounded":[24],"within":[25],"200ps.":[26],"At":[27],"loop":[29],"bandwidth":[30],"of":[31],"800Hz,":[32],"maximum":[34],"transient":[37],"slope":[38],"<4.5ns/ms.":[40],"The":[41,55],"jitter":[42],"generation":[43],"0.8ps":[45],"in":[46,52,63],"OC48":[48],"band":[49],"and":[50,69],"0.4ps":[51],"OC192":[53],"band.":[54],"16.32mm":[56],"<sup":[57],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[58],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">2</sup>":[59],"chip":[60],"fabricated":[62],"a":[64],"0.25mum":[65],"standard":[66],"CMOS":[67],"process":[68],"consumes":[70],"350mW":[71],"at":[72],"3.3V":[73]},"counts_by_year":[{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2013,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}