{"id":"https://openalex.org/W3215533141","doi":"https://doi.org/10.1109/isscc.2006.1696092","title":"An 8.4ns Column-Access 1.3Gb/s/pin DDR3 SDRAM with an 8:4 Multiplexed Data-Transfer Scheme","display_name":"An 8.4ns Column-Access 1.3Gb/s/pin DDR3 SDRAM with an 8:4 Multiplexed Data-Transfer Scheme","publication_year":2006,"publication_date":"2006-01-01","ids":{"openalex":"https://openalex.org/W3215533141","doi":"https://doi.org/10.1109/isscc.2006.1696092","mag":"3215533141"},"language":"en","primary_location":{"id":"doi:10.1109/isscc.2006.1696092","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isscc.2006.1696092","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5081923476","display_name":"Hironori Fujisawa","orcid":"https://orcid.org/0000-0002-8497-5846"},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"H. Fujisawa","raw_affiliation_strings":["ELPIDA Memory, Sagamihara, Japan"],"affiliations":[{"raw_affiliation_string":"ELPIDA Memory, Sagamihara, Japan","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5067261079","display_name":"S. Kubouchi","orcid":null},"institutions":[{"id":"https://openalex.org/I65143321","display_name":"Hitachi (Japan)","ror":"https://ror.org/02exqgm79","country_code":"JP","type":"company","lineage":["https://openalex.org/I65143321"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"S. Kubouchi","raw_affiliation_strings":["Hitachi ULSI Systems, Kokubunji, Japan"],"affiliations":[{"raw_affiliation_string":"Hitachi ULSI Systems, Kokubunji, Japan","institution_ids":["https://openalex.org/I65143321"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5056436703","display_name":"Koji Kuroki","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"K. Kuroki","raw_affiliation_strings":["ELPIDA Memory, Sagamihara, Japan"],"affiliations":[{"raw_affiliation_string":"ELPIDA Memory, Sagamihara, Japan","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5109526619","display_name":"Naho Nishioka","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"N. Nishioka","raw_affiliation_strings":["ELPIDA Memory, Sagamihara, Japan"],"affiliations":[{"raw_affiliation_string":"ELPIDA Memory, Sagamihara, Japan","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5015518079","display_name":"Yoshiro Riho","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Y. Riho","raw_affiliation_strings":["ELPIDA Memory, Sagamihara, Japan"],"affiliations":[{"raw_affiliation_string":"ELPIDA Memory, Sagamihara, Japan","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5089024226","display_name":"Hideyuki Noda","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"H. Noda","raw_affiliation_strings":["ELPIDA Memory, Sagamihara, Japan"],"affiliations":[{"raw_affiliation_string":"ELPIDA Memory, Sagamihara, Japan","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5063750786","display_name":"Ichiro Fujii","orcid":"https://orcid.org/0000-0003-0207-6415"},"institutions":[{"id":"https://openalex.org/I65143321","display_name":"Hitachi (Japan)","ror":"https://ror.org/02exqgm79","country_code":"JP","type":"company","lineage":["https://openalex.org/I65143321"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"I. Fujii","raw_affiliation_strings":["Hitachi ULSI Systems, Kokubunji, Japan"],"affiliations":[{"raw_affiliation_string":"Hitachi ULSI Systems, Kokubunji, Japan","institution_ids":["https://openalex.org/I65143321"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5068836168","display_name":"H. Yoko","orcid":null},"institutions":[{"id":"https://openalex.org/I65143321","display_name":"Hitachi (Japan)","ror":"https://ror.org/02exqgm79","country_code":"JP","type":"company","lineage":["https://openalex.org/I65143321"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"H. Yoko","raw_affiliation_strings":["Hitachi ULSI Systems, Kokubunji, Japan"],"affiliations":[{"raw_affiliation_string":"Hitachi ULSI Systems, Kokubunji, Japan","institution_ids":["https://openalex.org/I65143321"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5022882912","display_name":"Ryuuji Takishita","orcid":null},"institutions":[{"id":"https://openalex.org/I65143321","display_name":"Hitachi (Japan)","ror":"https://ror.org/02exqgm79","country_code":"JP","type":"company","lineage":["https://openalex.org/I65143321"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"R. Takishita","raw_affiliation_strings":["Hitachi ULSI Systems, Kokubunji, Japan"],"affiliations":[{"raw_affiliation_string":"Hitachi ULSI Systems, Kokubunji, Japan","institution_ids":["https://openalex.org/I65143321"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5080245088","display_name":"Taeko Ito","orcid":"https://orcid.org/0000-0002-3680-1024"},"institutions":[{"id":"https://openalex.org/I65143321","display_name":"Hitachi (Japan)","ror":"https://ror.org/02exqgm79","country_code":"JP","type":"company","lineage":["https://openalex.org/I65143321"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"T. Ito","raw_affiliation_strings":["Hitachi ULSI Systems, Kokubunji, Japan"],"affiliations":[{"raw_affiliation_string":"Hitachi ULSI Systems, Kokubunji, Japan","institution_ids":["https://openalex.org/I65143321"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5016804701","display_name":"Hiroki Tanaka","orcid":"https://orcid.org/0000-0002-8809-7147"},"institutions":[{"id":"https://openalex.org/I65143321","display_name":"Hitachi (Japan)","ror":"https://ror.org/02exqgm79","country_code":"JP","type":"company","lineage":["https://openalex.org/I65143321"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"H. Tanaka","raw_affiliation_strings":["Hitachi ULSI Systems, Kokubunji, Japan"],"affiliations":[{"raw_affiliation_string":"Hitachi ULSI Systems, Kokubunji, Japan","institution_ids":["https://openalex.org/I65143321"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5112211176","display_name":"M. Nakamura","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"M. Nakamura","raw_affiliation_strings":["ELPIDA Memory, Sagamihara, Japan"],"affiliations":[{"raw_affiliation_string":"ELPIDA Memory, Sagamihara, Japan","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":12,"corresponding_author_ids":["https://openalex.org/A5081923476"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.7522,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.77141824,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"557","last_page":"566"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/multiplexing","display_name":"Multiplexing","score":0.6167575120925903},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.6025776267051697},{"id":"https://openalex.org/keywords/column","display_name":"Column (typography)","score":0.5665249228477478},{"id":"https://openalex.org/keywords/cas-latency","display_name":"CAS latency","score":0.5046321153640747},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.5036124587059021},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.49152883887290955},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.47507137060165405},{"id":"https://openalex.org/keywords/memory-controller","display_name":"Memory controller","score":0.44975441694259644},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.43471601605415344},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.43333759903907776},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.30261242389678955},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.261261522769928},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.1158386766910553},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.10788732767105103},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.09013450145721436}],"concepts":[{"id":"https://openalex.org/C19275194","wikidata":"https://www.wikidata.org/wiki/Q222903","display_name":"Multiplexing","level":2,"score":0.6167575120925903},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.6025776267051697},{"id":"https://openalex.org/C2780551164","wikidata":"https://www.wikidata.org/wiki/Q2306599","display_name":"Column (typography)","level":3,"score":0.5665249228477478},{"id":"https://openalex.org/C189930140","wikidata":"https://www.wikidata.org/wiki/Q1112878","display_name":"CAS latency","level":4,"score":0.5046321153640747},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.5036124587059021},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.49152883887290955},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.47507137060165405},{"id":"https://openalex.org/C100800780","wikidata":"https://www.wikidata.org/wiki/Q1175867","display_name":"Memory controller","level":3,"score":0.44975441694259644},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.43471601605415344},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.43333759903907776},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.30261242389678955},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.261261522769928},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.1158386766910553},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.10788732767105103},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.09013450145721436},{"id":"https://openalex.org/C126042441","wikidata":"https://www.wikidata.org/wiki/Q1324888","display_name":"Frame (networking)","level":2,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isscc.2006.1696092","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isscc.2006.1696092","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.7300000190734863,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":1,"referenced_works":["https://openalex.org/W2103610846"],"related_works":["https://openalex.org/W2082939521","https://openalex.org/W2547220881","https://openalex.org/W3089341786","https://openalex.org/W2532617734","https://openalex.org/W1603816627","https://openalex.org/W2132401245","https://openalex.org/W2056138949","https://openalex.org/W1976244802","https://openalex.org/W2389333520","https://openalex.org/W2382635124"],"abstract_inverted_index":{"The":[0],"column":[1,68],"access":[2],"time":[3,47],"of":[4,32,70],"a":[5,11,42,56,67],"512Mb":[6],"DDR3":[7],"SDRAM":[8],"implemented":[9],"in":[10,45],"90nm":[12],"dual-gate":[13],"CMOS":[14],"process":[15],"is":[16,73],"reduced":[17],"by":[18],"2.9ns":[19],"to":[20,50],"8.4ns":[21],"through":[22],"an":[23],"8:4":[24],"multiplexed":[25],"data-transfer":[26],"scheme":[27],"that":[28],"enables":[29,41],"the":[30],"use":[31],"shielded":[33],"I/O":[34],"lines.":[35],"A":[36],"dual-clock":[37],"additive":[38],"latency":[39,69],"counter":[40],"30%":[43],"reduction":[44],"cycle":[46],"from":[48],"1.7":[49],"1.2ns.":[51],"By":[52],"combining":[53],"these":[54],"with":[55],"multiple":[57],"on-die-termination":[58],"merged":[59],"output":[60],"driver,":[61],"1.3Gb/s/pin":[62],"operation":[63],"at":[64],"1.36V":[65],"and":[66],"6":[71],"(CL6)":[72],"achieved":[74]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}