{"id":"https://openalex.org/W2024454156","doi":"https://doi.org/10.1109/isscc.2006.1696064","title":"A 64B CPU Pair: Dual- and Single-Processor Chips","display_name":"A 64B CPU Pair: Dual- and Single-Processor Chips","publication_year":2006,"publication_date":"2006-01-01","ids":{"openalex":"https://openalex.org/W2024454156","doi":"https://doi.org/10.1109/isscc.2006.1696064","mag":"2024454156"},"language":"en","primary_location":{"id":"doi:10.1109/isscc.2006.1696064","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isscc.2006.1696064","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5043375664","display_name":"E. Cohen","orcid":null},"institutions":[{"id":"https://openalex.org/I1341412227","display_name":"IBM (United States)","ror":"https://ror.org/05hh8d621","country_code":"US","type":"company","lineage":["https://openalex.org/I1341412227"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"E.B. Cohen","raw_affiliation_strings":["IBM, VT"],"affiliations":[{"raw_affiliation_string":"IBM, VT","institution_ids":["https://openalex.org/I1341412227"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5062191448","display_name":"Norman J. Rohrer","orcid":null},"institutions":[{"id":"https://openalex.org/I1341412227","display_name":"IBM (United States)","ror":"https://ror.org/05hh8d621","country_code":"US","type":"company","lineage":["https://openalex.org/I1341412227"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"N.J. Rohrer","raw_affiliation_strings":["IBM, VT"],"affiliations":[{"raw_affiliation_string":"IBM, VT","institution_ids":["https://openalex.org/I1341412227"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5024048378","display_name":"Peter A. Sandon","orcid":null},"institutions":[{"id":"https://openalex.org/I1341412227","display_name":"IBM (United States)","ror":"https://ror.org/05hh8d621","country_code":"US","type":"company","lineage":["https://openalex.org/I1341412227"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"P. Sandon","raw_affiliation_strings":["IBM, VT"],"affiliations":[{"raw_affiliation_string":"IBM, VT","institution_ids":["https://openalex.org/I1341412227"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5088080334","display_name":"M. Canada","orcid":null},"institutions":[{"id":"https://openalex.org/I1341412227","display_name":"IBM (United States)","ror":"https://ror.org/05hh8d621","country_code":"US","type":"company","lineage":["https://openalex.org/I1341412227"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"M. Canada","raw_affiliation_strings":["IBM, VT"],"affiliations":[{"raw_affiliation_string":"IBM, VT","institution_ids":["https://openalex.org/I1341412227"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5112840186","display_name":"C. Lichtenau","orcid":null},"institutions":[{"id":"https://openalex.org/I4210095996","display_name":"IBM (Germany)","ror":"https://ror.org/00pm7rm97","country_code":"DE","type":"company","lineage":["https://openalex.org/I1341412227","https://openalex.org/I4210095996"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"C. Lichtenau","raw_affiliation_strings":["IBM, Boeblingen, Germany"],"affiliations":[{"raw_affiliation_string":"IBM, Boeblingen, Germany","institution_ids":["https://openalex.org/I4210095996"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5041210657","display_name":"M.I. Ringler","orcid":null},"institutions":[{"id":"https://openalex.org/I1341412227","display_name":"IBM (United States)","ror":"https://ror.org/05hh8d621","country_code":"US","type":"company","lineage":["https://openalex.org/I1341412227"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"M. Ringler","raw_affiliation_strings":["IBM, VT"],"affiliations":[{"raw_affiliation_string":"IBM, VT","institution_ids":["https://openalex.org/I1341412227"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5085060473","display_name":"P. Kartschoke","orcid":null},"institutions":[{"id":"https://openalex.org/I1341412227","display_name":"IBM (United States)","ror":"https://ror.org/05hh8d621","country_code":"US","type":"company","lineage":["https://openalex.org/I1341412227"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"P. Kartschoke","raw_affiliation_strings":["IBM, VT"],"affiliations":[{"raw_affiliation_string":"IBM, VT","institution_ids":["https://openalex.org/I1341412227"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5059342649","display_name":"Raymond E. Floyd","orcid":"https://orcid.org/0000-0002-3814-7206"},"institutions":[{"id":"https://openalex.org/I1341412227","display_name":"IBM (United States)","ror":"https://ror.org/05hh8d621","country_code":"US","type":"company","lineage":["https://openalex.org/I1341412227"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"R. Floyd","raw_affiliation_strings":["IBM, VT"],"affiliations":[{"raw_affiliation_string":"IBM, VT","institution_ids":["https://openalex.org/I1341412227"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5036312608","display_name":"J. Heaslip","orcid":null},"institutions":[{"id":"https://openalex.org/I1341412227","display_name":"IBM (United States)","ror":"https://ror.org/05hh8d621","country_code":"US","type":"company","lineage":["https://openalex.org/I1341412227"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"J. Heaslip","raw_affiliation_strings":["IBM, VT"],"affiliations":[{"raw_affiliation_string":"IBM, VT","institution_ids":["https://openalex.org/I1341412227"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5076279783","display_name":"M. D. Ross","orcid":null},"institutions":[{"id":"https://openalex.org/I1341412227","display_name":"IBM (United States)","ror":"https://ror.org/05hh8d621","country_code":"US","type":"company","lineage":["https://openalex.org/I1341412227"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"M. Ross","raw_affiliation_strings":["IBM, VT"],"affiliations":[{"raw_affiliation_string":"IBM, VT","institution_ids":["https://openalex.org/I1341412227"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5022019097","display_name":"T. Pflueger","orcid":null},"institutions":[{"id":"https://openalex.org/I4210095996","display_name":"IBM (Germany)","ror":"https://ror.org/00pm7rm97","country_code":"DE","type":"company","lineage":["https://openalex.org/I1341412227","https://openalex.org/I4210095996"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"T. Pflueger","raw_affiliation_strings":["IBM, Boeblingen, Germany"],"affiliations":[{"raw_affiliation_string":"IBM, Boeblingen, Germany","institution_ids":["https://openalex.org/I4210095996"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5025023555","display_name":"Rolf Hilgendorf","orcid":null},"institutions":[{"id":"https://openalex.org/I4210156936","display_name":"IBM Research - Austin","ror":"https://ror.org/05gjbbg60","country_code":"US","type":"facility","lineage":["https://openalex.org/I1341412227","https://openalex.org/I4210114115","https://openalex.org/I4210156936"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"R. Hilgendorf","raw_affiliation_strings":["IBM, Austin, TX"],"affiliations":[{"raw_affiliation_string":"IBM, Austin, TX","institution_ids":["https://openalex.org/I4210156936"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5003944486","display_name":"P. McCormick","orcid":null},"institutions":[{"id":"https://openalex.org/I1341412227","display_name":"IBM (United States)","ror":"https://ror.org/05hh8d621","country_code":"US","type":"company","lineage":["https://openalex.org/I1341412227"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"P. McCormick","raw_affiliation_strings":["IBM, VT"],"affiliations":[{"raw_affiliation_string":"IBM, VT","institution_ids":["https://openalex.org/I1341412227"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5110855633","display_name":"G. Salem","orcid":null},"institutions":[{"id":"https://openalex.org/I1341412227","display_name":"IBM (United States)","ror":"https://ror.org/05hh8d621","country_code":"US","type":"company","lineage":["https://openalex.org/I1341412227"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"G. Salem","raw_affiliation_strings":["IBM, VT"],"affiliations":[{"raw_affiliation_string":"IBM, VT","institution_ids":["https://openalex.org/I1341412227"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5041881668","display_name":"Jerome T. Connor","orcid":"https://orcid.org/0000-0002-7141-6260"},"institutions":[{"id":"https://openalex.org/I1341412227","display_name":"IBM (United States)","ror":"https://ror.org/05hh8d621","country_code":"US","type":"company","lineage":["https://openalex.org/I1341412227"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"J. Connor","raw_affiliation_strings":["IBM, VT"],"affiliations":[{"raw_affiliation_string":"IBM, VT","institution_ids":["https://openalex.org/I1341412227"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5110117248","display_name":"S. Gei\u00dfler","orcid":null},"institutions":[{"id":"https://openalex.org/I1341412227","display_name":"IBM (United States)","ror":"https://ror.org/05hh8d621","country_code":"US","type":"company","lineage":["https://openalex.org/I1341412227"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"S. Geissler","raw_affiliation_strings":["IBM, VT"],"affiliations":[{"raw_affiliation_string":"IBM, VT","institution_ids":["https://openalex.org/I1341412227"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5013052979","display_name":"D. Thygesen","orcid":null},"institutions":[{"id":"https://openalex.org/I1341412227","display_name":"IBM (United States)","ror":"https://ror.org/05hh8d621","country_code":"US","type":"company","lineage":["https://openalex.org/I1341412227"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"D. Thygesen","raw_affiliation_strings":["IBM, VT"],"affiliations":[{"raw_affiliation_string":"IBM, VT","institution_ids":["https://openalex.org/I1341412227"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":17,"corresponding_author_ids":["https://openalex.org/A5043375664"],"corresponding_institution_ids":["https://openalex.org/I1341412227"],"apc_list":null,"apc_paid":null,"fwci":2.2299,"has_fulltext":false,"cited_by_count":9,"citation_normalized_percentile":{"value":0.87109416,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"333","last_page":"342"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9771999716758728,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9771999716758728,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9614999890327454,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9564999938011169,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/microprocessor","display_name":"Microprocessor","score":0.6706887483596802},{"id":"https://openalex.org/keywords/pipeline-burst-cache","display_name":"Pipeline burst cache","score":0.6664978265762329},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6373260021209717},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.59611976146698},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.5896035432815552},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.5446025133132935},{"id":"https://openalex.org/keywords/dual","display_name":"Dual (grammatical number)","score":0.5438599586486816},{"id":"https://openalex.org/keywords/microarchitecture","display_name":"Microarchitecture","score":0.49167948961257935},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.4896290898323059},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4871220588684082},{"id":"https://openalex.org/keywords/register-file","display_name":"Register file","score":0.48149192333221436},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4266943633556366},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.39578625559806824},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.3939019739627838},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.28491321206092834},{"id":"https://openalex.org/keywords/cache-coloring","display_name":"Cache coloring","score":0.1455276906490326}],"concepts":[{"id":"https://openalex.org/C2780728072","wikidata":"https://www.wikidata.org/wiki/Q5297","display_name":"Microprocessor","level":2,"score":0.6706887483596802},{"id":"https://openalex.org/C157547923","wikidata":"https://www.wikidata.org/wiki/Q7197276","display_name":"Pipeline burst cache","level":5,"score":0.6664978265762329},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6373260021209717},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.59611976146698},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.5896035432815552},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.5446025133132935},{"id":"https://openalex.org/C2780980858","wikidata":"https://www.wikidata.org/wiki/Q110022","display_name":"Dual (grammatical number)","level":2,"score":0.5438599586486816},{"id":"https://openalex.org/C107598950","wikidata":"https://www.wikidata.org/wiki/Q259864","display_name":"Microarchitecture","level":2,"score":0.49167948961257935},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.4896290898323059},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4871220588684082},{"id":"https://openalex.org/C117280010","wikidata":"https://www.wikidata.org/wiki/Q180944","display_name":"Register file","level":3,"score":0.48149192333221436},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4266943633556366},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.39578625559806824},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.3939019739627838},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.28491321206092834},{"id":"https://openalex.org/C201148951","wikidata":"https://www.wikidata.org/wiki/Q5015976","display_name":"Cache coloring","level":4,"score":0.1455276906490326},{"id":"https://openalex.org/C124952713","wikidata":"https://www.wikidata.org/wiki/Q8242","display_name":"Literature","level":1,"score":0.0},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isscc.2006.1696064","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isscc.2006.1696064","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.800000011920929}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W1497661995","https://openalex.org/W1571544561","https://openalex.org/W1572222871","https://openalex.org/W2098985322","https://openalex.org/W2124256021","https://openalex.org/W4285719527","https://openalex.org/W6634194400","https://openalex.org/W6634354345"],"related_works":["https://openalex.org/W2540018280","https://openalex.org/W4253895162","https://openalex.org/W4251089459","https://openalex.org/W2090169195","https://openalex.org/W2111412181","https://openalex.org/W1547865754","https://openalex.org/W2102384429","https://openalex.org/W2276000909","https://openalex.org/W4250432526","https://openalex.org/W2101536355"],"abstract_inverted_index":{"Two":[0],"Powertrade-architecture":[1],"64b":[2],"microprocessor":[3],"chips":[4],"are":[5],"fabricated":[6],"in":[7],"90nm":[8],"dual":[9],"strained-silicon":[10],"SOI":[11],"technology.":[12],"The":[13,35],"dual-processor":[14],"chip":[15,37],"has":[16],"split":[17],"clock":[18],"domains":[19],"and":[20,29,43],"power":[21],"planes,":[22],"1":[23],"MB":[24],"L2":[25],"cache":[26,44],"per":[27],"core":[28,42],"a":[30],"shared":[31],"processor":[32],"interconnect":[33],"bus.":[34],"single-processor":[36],"shares":[38],"the":[39],"dual's":[40],"basic":[41],"design":[45]},"counts_by_year":[{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}